Sony SLV-7700KME, Service Manual

Page: 90 / 135

6-10
Pin No.
Pin Name
I/O
Function
CAS signal. Connect to the CAS pin of the DRAM so as to control the
36
XCAS2
O
lo
w
er b
ytes of the upper wor
d
(256K to 512K-1) f
or the 256Kw
×
16b
/MA9
×
2 DRAM structure. /Address signal pin. Connect to the DRAM address
pin with the same number
.
CAS signal. Connect to the CAS pin of the DRAM so as to control the
37
XCAS0
O
lo
w
er b
ytes (MD0 to MD7) f
or 256Kw
×
16b and 512Kw
×
8b
×
2 DRAM str
uctures,
and to contr
ol the lo
wer b
ytes of the lo
wer wor
d
(0 to 256K-1) for the 256Kw
×
16b
×
2 DRAM structure.
38
MD7
I/O
39
MD8
I/O
40
MD6
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the
4
1
M
D
9
I/
O
lo
w
er and upper bytes of the da
ta correspond to the CAS0 to CAS3 controls.
42
MD5
I/O
43
MD10
I/O
44
VDD
–
+5V po
wer suppl
y.
45
VSS
–
GND.
46
MD4
I/O
47
MD11
I/O
48
MD3
I/O
49
MD12
I/O
50
MD2
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the
51
MD13
I/O
lo
w
er
and upper bytes of the da
ta correspond to the CAS0 to CAS3 controls.
52
MD1
I/O
53
MD14
I/O
54
MD0
I/O
55
MD15
I/O
56
XOSDEN
I
OSD enable signal.
57
OSDB
I
OSD da
ta input pin.
When the XOSDEN input is L, the color r
egister
ed
58
OSDG
I
in the r
egister specif
ied by this 3 inputs (3 bits) is output as the ima
g
e
59
OSDR
I
data. (Connected to ground)
60
VDD
–
+5V po
wer suppl
y.
61
VSS
–
GND. V
ideo output enable signal pin.
When set to
‘L
’, ena
bles the image da
ta
62
XV
OE
I
output and DCLK output.
When set to ‘H’,
disa
bles (high impedance).
Output contr
ol can also be perf
or
med by writing in the re
g
ister
.
63
R/Cr0
O
64
R/Cr1
O
Output pin of the R or Cr signal of the image data. MSB is R/Cr7.
65
R/Cr2
O
Synchronizes with DCLK.
66
R/Cr3
O
6-1
1. MPEG DECODER PORT FUNCTION DESCRIPTION (CD-169 BOARD IC305 CXD1852Q)
Pin No.
Pin Name
I/O
Function
1
VSS
–
GND.
2
XTL0O
O
V
ideo decoder master cloc
k pin. Input the XTL0I c
loc
k or connect an
oscillator between XTL0I and XTL0O
.
T
he recommended fr
equencies
3
XTL0I
I
ar
e 27 MHz, 28.6363 MHz (NTSC 8fsc),
and 35.4686 MHz (P
AL 8fsc).
4
VDD
–
+5V po
wer suppl
y.
5
HA2
I
A
ddr
ess input pin. In some cases,
ser
v
es as the control signal and data
6
HA3
I
input according to the setting of the control mode.
7
HD0
I/O
8
HD1
I/O
9
HD2
I/O
10
HD3
I/O
Data input/output.
11
HD4
I/O
12
HD5
I/O
13
HD6
I/O
14
VDD
–
+5V po
wer suppl
y.
15
VSS
–
GND.
16
HD7
I/O
Data input/output.
17
MA3
O
18
MA4
O
1
9
M
A
2
O
A
ddress signal pin. Connect to the DRAM ad
dr
ess pin with the same n
umber
.
20
MA5
O
21
MA1
O
22
VSS
–
GND.
2
3
M
A
6
O
A
ddress signal pin. Connect to the DRAM ad
dr
ess pin with the same n
umber
.
24
MA0
O
25
BC
I
26
TCKI
I
27
TDI
I
F
or test.
28
TEN
AI
I
29
TDO
I
30
VST
I
F
or test. (Connect to gr
ound)
31
VSS
–
GND.
32
MA7
O
Address signal pin. Connect to the DRAM address pin with the same
33
MA8
O
n
umber
.
34
XRAS
O
RAS signal pin. Connect to the RAS pin of the DRAM. Same for the 256Kw
×
16b, 256Kw
×
16b
×
2, and 512Kw
×
8b
×
2 DRAM structures.
35
XMWE
O
WE signal pin. Connect to the
WE pin of the DRAM.