46
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MAIN BOARD IC711 CXD1095R (EXPANDER)
Pin No.
Pin Name
I/O
Description
1
AK1
O
2
AK2
O
3
MON3
O
4
MON4
O
Monitor signal output terminal Not used (open)
5
MON5
O
6
MON6
O
7
MON7
O
8
VSS
—
Ground terminal
9
WADCE
O
Watermark signal output to the RF AD (IC708)
10
TEST
O
Test signal output to the DSD decoder (IC703) “H”:active
11
WMGC0
O
RF gain control for watermark signal output to the RF AD (IC708)
12
WMGC1
O
RF gain control for watermark signal output to the RF AD (IC708)
13
SHR RST
O
Reset signal output to the DSD decoder (IC703)
14
SHR MUTE
O
Mute signal output to the DSD decoder (IC703)
15
SHR LT
O
Latch pulse signal output to the DSD decoder (IC703)
16
—
O
Not used (open)
17
NC
—
Not used (open)
18
FWON
O
FWON signal output to the ARP (IC702)
19
MD2
O
CD-TX mute signal output to the ARP (IC702)
20
MUTE
O
CD-DA mute signal output to the ARP (IC702)
21
ARP RST
O
Reset signal output to the ARP (IC702)
22
DFCT
I
DFCT signal input from the ARP (IC702)
23
VSS
—
Ground terminal
24
VDD
—
Power supply terminal (+5V)
25
NORF
I
NORF signal input from the ARP (IC702)
26
LOCK
I
Lock signal input from the ARP (IC702)
27
FIL SET
I
Filter select signal input from the STANDARD/CUSTOM switch (S173) “L”:CUSTOM “H”
:STANDARD
28
D0
I/O
29
D1
I/O
Two-way data bus with the CPU (IC701)
30
D2
I/O
31
NC
—
Not used (open)
32
NC
—
Not used (open)
33
D3
I/O
34
D4
I/O
35
D5
I/O
Two-way data bus with the CPU (IC701)
36
D6
I/O
37
D7
I/O
38
XCLR
I
Clear signal input terminal (pull up)
39
XDIS
I
Reset signal input from the ARP (IC702)
40
VSS
—
Ground terminal
41
XWR
I
Strobe signal input from the CPU (IC701)
42
XRD
I
Strobe signal input from the CPU (IC701)
43
XCS
I
Chip enable signal input from the CPU (IC701)