Sony PlayStationPortable, Documentation

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4 CPU OVERVIEW 27
Pair Columns Pair Rows
C000 C010 C020 C030
.... .... .... ....
C002 C012 C022 C032
.... .... .... ....
R000 .... R020 ....
R001 .... R021 ....
R002 .... R022 ....
R003 .... R023 ....
2*2 Matrix 2*2 Transpose Matrix
M000 .... M020 ....
.... .... .... ....
M002 .... M022 ....
.... .... .... ....
E000 .... E020 ....
.... .... .... ....
E002 .... E022 ....
.... .... .... ....
Repeat all of the above with the other 7 blocks of registers. Just change the first digit of the register names to work on a different set
4.5 Instruction Format
Every CPU instruction consists of a single word (32 bits) aligned on a word boundary and the major instruction formats are shown here:
I-Type (Immediate)
op rs rt immediate
oooooo sssss ttttt iiiiiiiiiiiiiiii
31 26 25 21 20 16 15 0
J-Type (Jump)
op target
oooooo tttttttttttttttttttttttttt
31 26 25 0
R-Type (Register)
op rs rt rd shamt func
oooooo sssss ttttt ddddd aaaaa ffffff
31 26 25 21 20 16 15 11 10 6 5 0
where:
op 6-bit operation code
rs 5-bit source register specifier
rt 5-bit target (source/destination) register or branch condition
immediate 16-bit immediate, branch displacement or address displacement
target 26-bit jump target address
rd 5-bit destination register specifier
shamt 5-bit shift amount
func 6-bit function field
4.6 MIPS Instructions
Mnemonic Opcode
op rs rt offset
Description
lw rt, offset(rs) 0x8c000000 100011 sssss ttttt oooooooooooooooo
LoadWord Relative to Address in General Purpose Register
sw rt, offset(rs) 0xac000000 101011 sssss ttttt oooooooooooooooo
StoreWord Relative to Address in General Purpose Register
Mnemonic Opcode
op rs rt immediate
Description
addiu rt,rs,immediate 0x24000000 001001 sssss ttttt iiiiiiiiiiiiiiii
Add Immediate Unsigned Word