MEX-N5100BE/N5100BT/N5150BT
43
Pin No.
Pin Name
I/O
Description
61
DAO5
O
Audio signal (sub-ch) output to the electrical volume
62
DVSS5
-
Ground terminal
63
VDD1_3
-
Power supply terminal (+1.5V)
64
VSS_2
-
Ground terminal
65
XVSS3
-
Ground terminal
66
XI
I
System clock input terminal (16.9344 MHz)
67
XO
O
System clock output terminal (16.9344 MHz)
68
XVDD3
-
Power supply terminal (+3.3V)
69
ADVDD3
-
Power supply terminal (+3.3V)
70
ADIN1
I
Audio signal (L-ch) input from the electrical volume
71
ADVREFL
O
Reference voltage output terminal
72
ADVCM
O
Reference voltage output terminal
73
ADVREFH
O
Reference voltage output terminal
74
ADIN2
I
Audio signal (R-ch) input from the electrical volume
75
ADVSS3
-
Ground terminal
76
MS
I
Microprocessor interface mode selection signal input terminal
“L”: serial interface, “H”: parallel interface Fixed at “L” in this unit
77, 78
BUS0, BUS1
I/O
Serial data input/output terminal Not used
79
BUS2
O
Serial data output to the system controller
80
BUS3
I
Serial data input from the system controller
81
BUCK
I
Serial data transfer clock signal input from the system controller
82
CCE
I
Chip enable signal input from the system controller
83
VDD3_2
-
Power supply terminal (+3.3V)
84
VSS_3
-
Ground terminal
85
RST
I
Reset signal input from the system controller “L”: reset
86
VDD1_4
-
Power supply terminal (+1.5V)
87
PIO0
O
Interrupt signal output to the system controller
88
PIO1
O
Request signal output to the system controller
89
PIO2
I
Gate signal input from the system controller
90
PIO3
I
Audio data input from the system controller
91
PIO4
I
Bit clock signal input from the system controller
92
PIO5
I
L/R sampling clock signal input from the system controller
93
PIO6
I
Muting on/off control signal input from the system controller “L”: muting on
94
PIO7
O
Zero data detection signal output to the system controller
95
PIO8/CDMON0
O
Serial data output to the system controller
96
PIO9/CDMON1
I
Serial data transfer clock signal input from the system controller
97
TEST
I
Test mode setting terminal Normally
fi
xed at “L”
98
PDO
O
EFM and PLCK phase difference signal output terminal
99
TMAX
O
TMAX detection result output terminal
100
LPFN
I
PLL circuit low-pass
fi
lter ampli
fi
er inversion input terminal
