Sony MDX-C8900R, Service Manual

Page: 67 / 88

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Pin No. Pin Name I/O Function
68 SUBCE O Chip enable signal output to the sub electrical volume (IC403) “H” active
69
FLASH-W
I
Internal flash memory data write mode detection signal input terminal “L”: data write mode
Not used (fixed at “H” in this set)
70 RDSSI I
Serial data input from the RDS decoder (IC701)
71 RDSCKO O
Serial data reading clock signal output to the RDS decoder (IC701)
72 RC-IN1
I Rotary remote commander shift key input terminal “L”: shift
73 X1A O
Sub system clock output terminal (32 kHz)
74 X0A I
Sub system clock input terminal (32 kHz)
75 DAVN I
Data transmit completed detect signal input from the RDS decoder (IC701) “H” active
76 KEYACK
I
Input of acknowledge signal for the key entry Acknowledge signal is input to accept function
and eject keys in the power off status On at input of “H”
77 BU-IN
I
Battery detect signal input from the SONY bus interface (IC504) and battery detect circuit
“L” is input at low voltage
78 ILL IN
I
Auto dimmer control illumination line detection signal input terminal
“L” is input at dimmer detection
79
TEL-ATT I Telephone muting signal input terminal At input of “L”, the signal is attenuated by –20 dB
80 NOSESW I
Front panel block remove/attach detection switch (SW503) signal input terminal
“L”: front panel is attached
81 ACC IN
I Accessory detect signal input terminal “L”: accessory on
82 to 85
TIR-D0 to TIR-D3
I/O
Two-way data bus with the MSM6688GS (IC703)
86 HSTX I
Hardware standby input terminal “L”: hardware standby mode Reset signal input in this set
87 MD2 I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
88 MD1 I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
89 MD0 I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
90 RESET I
System reset signal input from the reset signal generator (IC505) and reset switch (SW701)
“L” is input for several 100 msec after power on, then it changes to “H”
91 VSS —
Ground terminal
92 X0
I Main system clock input terminal (3.68 MHz)
93 X1
O Main system clock output terminal (3.68 MHz)
94 VCC —
Power supply terminal (+5V)
95 TIR-BUSY I
Busy detection signal input from the MSM6688GS (IC703)
“H” is output while MSM6688GS (IC703) is executing a command
96 TIR-WR O
Data write strobe signal output to the MSM6688GS (IC703)
“L” is output when data (D0 to D3) are output to the MSM6688GS (IC703)
97 TIR-CE O
98 TIR-CE O
99 TIR-RES O Reset signal output to the MSM6688GS (IC703) “H”: reset
100 TIR-PDOWN O Power down control signal output to the MSM6688GS (IC703) “L”: power down
101 TIR-RD O
Data read strobe signal output to the MSM6688GS (IC703)
“L” is output when data (D0 to D3) are output to the MSM6688GS (IC703)
102 MTLIN I Not used (fixed at “L”)
103 AM STIN I Not used (fixed at “L”)
104 LOCK
I
Mini-disc lock detection signal input from the MD mechanism controller (IC501) “H”: lock
CLV lock status input in test mode
105 to108 POS0 to POS3 I Not used (fixed at “L”)
109 MD-ATT I
The audio muting control signal is input from the MD mechanism controller (IC501), and output
to ATT (pin
^∞
)
Chip enable signal output to the MSM6688GS (IC703)
TIR-WR (pin
(§
) or TIR-RD (pin
`⁄‚⁄
) is accepted when CE is “L” or CE is “H” respectively
TIR-WR (pin
(§
) or TIR-RD (pin
`⁄‚⁄
) is not accepted when CE is “H” or CE is “L” respectively