Sony HDCAM HDW-750, Maintenance Manual

Page: 168 / 442

2-14
HDW-750 V2
RF RATE CONVERTER
—TOP VIEW—
132 130 125 120 115 110 105 100 95 90 89
88
85
80
75
70
65
60
55
50
45
133
135
140
145
150
155
160
165
170
175
176
1 5
10 15 20 25 30 35 40 44
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PIN
NO.
I/O SIGNAL
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
PIN
NO.
I/O
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
SIGNAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RF_START
TRACK_START
V
CCE5
ENC_CTRL_1
ENC_CTRL_0
GND
CLS
V
CC
TCLK
TCKE
REC_EXTERNAL
V
CCEI
REC_ENABLE_AC
V
CC
REC_DATA_ACP
REC_DATA_ACN
GND
REC_DATA_BDP
REC_DATA_BDN
BIAS_EX
CLK_RECI_P
CLK_RECI_N
V
CCEI
PBI
TTST
RESET
VPD
GND
CLK_HEADI
TBST
V
CC
FRAME
V
CCEI
TXCS
RF_TRACK_START
TMS_1
V
CC
TMS_0
GND
CLK_MIF
P_UP_SEQ_MD
TDQM_1
TDQM_0
GND
V
CCE5
MONITOR_0
MONITOR_1
MONITOR_2
MONITOR_3
GND
V
CCEI
MONITOR_4
MONITOR_5
MONITOR_6
MONITOR_7
V
CCE5
MONITOR_8
MONITOR_9
TDO
TDI
GND
TMS
TCK
TRST
GND
V
CCE5
GND
V
CCE5
REC_EN_PORT1_E
REC_EN_PORT1_F
REC_EN_PORT1_G
GND
REC_EN_PORT1_H
CLK_HEADI1_L
REC_DT_PORT1_E
REC_DT_PORT1_F
V
CCE5
V
CCE5
REC_DT_PORT1_G
REC_DT_PORT1_H
EE_SW_PORT1_E
V
CCEI
GND
EE_SW_PORT1_F
EE_SW_PORT1_G
EE_SW_PORT1_H
V
CCE5
GND
TA_10
TA_9
TA_8
TA_7
TA_6
GND
EE_SW_PORT2_A
EE_SW_PORT2_B
EE_SW_PORT2_C
EE_SW_PORT2_D
V
CCE5
V
CCEI
EE_SW_PORT2_E
EE_SW_PORT2_F
EE_SW_PORT2_G
EE_SW_PORT2_H
GND
REC_DT_PORT2_A
REC_DT_PORT2_B
REC_DT_PORT2_C
REC_DT_PORT2_D
REC_DT_PORT2_E
V
CCE5
REC_DT_PORT2_F
REC_DT_PORT2_G
REC_DT_PORT2_H
CLK_HEADI_2
GND
REC_EN_PORT2_A
REC_EN_PORT2_B
REC_EN_PORT2_C
REC_EN_PORT2_D
V
CCEI
REC_EN_PORT2_E
REC_EN_PORT2_F
REC_EN_PORT2_G
REC_EN_PORT2_H
TA_5
GND
TA_4
TA_3
TA_2
TA_1
TA_0
V
CCE5
GND
EE_SW_PORT1_A
EE_SW_PORT1_B
EE_SW_PORT1_C
GND
V
CCEI
EE_SW_PORT1_D
REC_DT_PORT1_A
REC_DT_PORT1_B
REC_DT_PORT1_C
V
CCE5
REC_DT_PORT1_D
CLK_HEADI1_R
REC_EN_PORT1_A
REC_EN_PORT1_B
GND
REC_EN_PORT1_C
REC_EN_PORT1_D
GND
V
CCE5
XCPUSTRB
XCPUCS
CPUSTAT_0
CPUSTAT_1
CLK_CPU
GND
GND
V
CCE5
V
CCE5
B_CPUAD_0
B_CPUAD_1
V
CCE5
B_CPUAD_2
B_CPUAD_3
B_CPUAD_4
GND
V
CCEI
GND
B_CPUAD_5
V
CCE5
B_CPUAD_6
B_CPUAD_7
EVE_SEL
O
O
—
O
O
—
I
—
—
—
I
—
I
—
I
I
—
I
I
O
I
I
—
I
—
I
I
—
I
—
—
I
—
—
I
—
—
—
—
I
I
—
—
—
—
O
O
O
O
—
—
O
O
O
O
—
O
O
—
—
—
—
—
—
—
—
—
—
O
O
O
—
O
O
O
O
—
—
O
O
O
—
—
O
O
O
—
—
I
I
I
I
I
—
O
O
O
O
—
—
O
O
O
O
—
O
O
O
O
O
—
O
O
O
O
—
O
O
O
O
—
O
O
O
O
I
—
I
I
I
I
I
—
—
O
O
O
—
—
O
O
O
O
—
O
O
O
O
—
O
O
—
—
I
I
I
I
I
—
—
—
—
I/O
I/O
—
I/O
I/O
I/O
—
—
—
I/O
—
I/O
I/O
O
INPUTS
CLK_CPU
CLK_HEADI
CLK_MIF
CLK_RECI_N
CLK_RECI_P
CLS
CPUSTAT_0, CPUSTAT_1
FRAME
PBI
P_UP_SEQ_MD
REC_DATA_ACN
REC_DATA_ACP
REC_DATA_BDN
REC_DATA_BDP
REC_ENABLE_AC
REC_EXTERNAL
RESET
RF_TRACK_START
TA_0 - TA_10
VPD
XCPUCS, XCPUSTRB
OUTPUTS
BIAS_EX
CLK_HEADI1_L
CLK_HEADI1_R
CLK_HEADI_2
EE_SW_PORT1_A - EE_SW_PORT1_H
EE_SW_PORT2_A - EE_SW_PORT2_H
ENC_CTRL_0
ENC_CTRL_1
EVE_SEL
MONITOR_0 - MONITOR_9
REC_DT_PORT1_A - REC_DT_PORT1_H
REC_DT_PORT2_A - REC_DT_PORT2_H
REC_EN_PORT1_A - REC_EN_PORT1_H
REC_EN_PORT2_A - REC_EN_PORT2_H
RF_START
TRACK_START
INPUTS/OUTPUTS
B_CPUAD_0 - B_CPUAD_7
OTHERS
TCK, TDI, TDO, TMS, TRST
TCKE, TCLK
TDQM_0, TDQM_1
TMS_0, TMS_1
TBST, TTST
TXCS
V
CCE5
V
CCEI
: CPU CLOCK (UNDER 27 MHz)
: DRUM HEAD FREQUENCY CLOCK
: DRAM CLOCK
: ECC ENC CLOCK
: ECC ENC CLOCK
: DRAM TEST
: CPU CONTROL
: ECC ENC SYNCHRONIZE FRAME/FIELD PULSE
: DRAM TEST CONTROL
: DRAM INITIALIZE (WHEN LOW:INITIALIZE)
: REC DATA ACN (ECC ENC DATA)
: REC DATA ACP (ECC ENC DATA)
: REC DATA BDN (ECC ENC DATA)
: REC DATA BDP (ECC ENC DATA)
: REC ENABLE AC
: REC EXTERNAL
: RESET
: DRUM HEAD SYNCHRONIZE TRACK START
: DRAM TEST
: VPD
: CPU CONTROL
: LVDS BIAS
: PELIPHERAL CLOCK HEAD1 LEFT
: PELIPHERAL CLOCK HEAD1 RIGHT
: PELIPHERAL CLOCK HEAD2
: EE SWITCH PORT1
: EE SWITCH PORT2
: ENC CONTROL (BD_SEL/ TRACK_START)
: ENC CONTROL (AC_SEL/ RF_START)
: AC SEL FOR EVE
: MONITOR
: REC DT PORT1
: REC DT PORT2
: REC EN PORT1
: REC EN PORT2
: RF START FOR TEST
: TRACK START FOR TEST
: CPU DATA
: JTAG
: DRAM TEST
: DRAM TEST
: DRAM TEST
: DRAM TEST CONTROL
: DRAM TEST
: ADDITIONAL POWER SUPPLY (3.3 V)
: POWER SUPPLY (INTERNAL : 2.5 V)
CXD9132R (SONY)
IC