Sony HDCAM HDW-750, Maintenance Manual

Page: 170 / 442

2-16
HDW-750 V2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
64K (8192 x 8)-BIT EEPROM
—TOP VIEW—
RDY/
BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V
CC
WE
RES
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
INPUTS
A0 - A12
CE
OE
RDY/
BUSY
RES
WE
INPUTS/OUTPUTS
I/O0 - I/O7
: ADDRESS
: CHIP ENABLE
: OUTPUT ENABLE
: READY BUSY
: RESET
: WRITE ENABLE
: DATA
1
2
3
4
5
6
7
8
GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CS
/LD
SCK
16
15
14
13
12
11
10
9
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CLR
D
OUT
D
IN
D/A CONVERTER
—TOP VIEW—
INPUTS
CLR
CS
/LD
D
IN
REF
SCK
OUTPUTS
D
OUT
V
OUT A
- V
OUT H
: ASYNCHRONOUS CLEAR
: SERIAL INTERFACE CHIP SELECT/LOAD
: SERIAL INTERFACE DATA
: REFERENCE VOLTAGE
: SERIAL INTERFACE CLOCK
: SERIAL INTERFACE DATA
: DAC ANALOG VOLTAGE
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
V
OUT A
V
OUT D
REF
V
OUT C
V
OUT B
V
OUT H
V
OUT E
CLR
V
OUT F
V
OUT G
CS
/LD
SCK
D
OUT
D
IN
2
3
4
5
6
7
8
9
10
12
11
13
14
15
1
2
4
3
GND
RESET
V
CC
SRT
VOLTAGE MONITOR
—TOP VIEW—
INPUT
SRT
OUTPUT
RESET
: SET RESET TIMEOUT
: ACTIVE-LOW RESET
HN58V66AFP-10Z (HITACHI)
LTC1660CGN-E2 (LINEAR TECH)
MAX821RUS-T (MAXIM)
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9
10 11
1
2
3
4
5
6
7
8
9
10
11
I/O
I/O
—
I
I
I
O
I
I
I
I
D +
D _
V
CC
TEST1
TEST2
XIN
XOUT
CS
RD
WR
RESET
12
13
14
15
16
17
18
19
20
21
22
O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
INTR
D15
D14
D13
D12
GND
V
CC
D11
D10
D9
D8
23
24
25
26
27
28
29
30
31
32
33
I
I
I
I
I
I
I
I
I
I
I
ALE
ADSEL
A7
A6
A5
A4
A3
A2
A1
A0
DACK
34
35
36
37
38
39
40
41
42
43
44
O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
DREQ
AD7
AD6
AD5
AD4
GND
V
CC
AD3
AD2
AD1
AD0
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
USB DEVICE CONTROLLER
—TOP VIEW—
INPUTS
A0 - A7
ADSEL
ALE
CS
DACK
RD
RESET
TEST1, TEST2
WR
XIN
OUTPUTS
DREQ
INTR
XOUT
INPUTS/OUTPUTS
AD0 - AD7
D + , D _
D8 - D15
: ADDRESS
: ADDRESS INPUT FORMAT SELECT
: ADDRESS LATCH ENABLE
: CHIP SELECT
: DMA ACKNOWLEDGEMENT
: READ
: RESET
: TEST
: WRITE
: CRYSTAL OR EXTERNAL CLOCK
: DMA REQUEST
: INTERRUPT REQUEST
: CRYSTAL FEEDBACK
: DATA BUS (LSB)/ADDRESS (INPUT)
: DIFFERENTIAL USB DATA
: DATA BUS (MSB)
APPLICATION
INTERFACE
STATUS/
CONTROL
ENDPOINT
FIFO
AND
8-BYTE
SETUP
REGISTER
PROTOCOL
ENGINE
DPLL OSCILLATOR
USB
TRANSCEIVER
XIN
6
CS
8
D8 - D15
AD0 - AD7
22 - 19, 16 - 13
44 - 41, 38 - 35
A0 - A7
32 - 25
RD
9
WR
10
RESET
11
INTR
12
DREQ
34
DACK
33
XOUT
7
D
+
1
D _
2
ML60851BTB (OKI)
ML60851CTB
IC