Sony HDCAM HDW-750, Maintenance Manual

Page: 175 / 442

2-21
HDW-750 V2
81
85
90
95
100
TIMECODE DELAY CONTROLLER
—TOP VIEW—
50
45
40
35
31
80 75 70 65 60 55 51
1 5
10 15 20 25 30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
—
I
—
GND
I/O,GCK1
I/O
I/O,TDI
I/O,TCK
I/O,TMS
I/O
I/O
I/O
I/O
GND
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,GCK2
M1
GND
M0
V
CC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
PWRDWN
I/O,GCK3
I/O(HDC)
I/O
I/O(
LDC
)
I/O
I/O
I/O
I/O
I/O
I/O(
INIT
)
V
CC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,GCK4
GND
DONE
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
—
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
—
V
CC
PROGRAM
I/O(D7)
I/O,GCK5
I/O(D6)
I/O
I/O(D5)
I/O
I/O
I/O
I/O(D4)
I/O
V
CC
GND
I/O(D3)
I/O
I/O
I/O(D2)
I/O
I/O(D1)
I/O
I/O(D0,DIN)
I/O,GCK6,DOUT
CCLK
V
CC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O,TDO
GND
I/O
I/O,GCK7
I/O(CS1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,GCK8
V
CC
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
INPUTS
CCLK
CS1
D0 - D7
DIN
GCK1 - GCK8
M0, M1
PROGRAM
PWRDWN
TDI
TCK
TMS
OUTPUTS
DOUT
HDC
LDC
TDO
INPUTS/OUTPUTS
DONE
INIT
I/O
: CONFIGURATION CLOCK
: SERIAL-ENABLE SIGNAL FOR DAISY-CHAINING (DURING EXPRESS CONFIGURATION)
: RECEIVE CONFIGURATION DATA (DURING EXPRESS CONFIGURATION)
: SERIAL CONFIGURATION DATA RECEIVING DATA ON THE RISING EDGE OF CCLK
(DURING SLAVE SERIAL OR MASTER SERIAL CONFIGURATION)
: GLOBAL
: MODE
: FORCE THE FPGA TO CLEAR ITS CONFIGURATION MEMORY
: FORCE THE FPGA INTO THE POWER DOWN STATE AND REDUCE POWER CONSUMPTION
: TEST DATA (WHEN BOUNDARY SCAN IS USED)
: TEST CLOCK (WHEN BOUNDARY SCAN IS USED)
: TEST MODE SELECT (WHEN BOUNDARY SCAN IS USED)
: SERIAL CONFIGURATION DATA DRIVING THE DIN OF DAISY-CHAINED SLAVE FPGAS
(DURING SLAVE SERIAL OR MASTER SERIAL CONFIGURATION)
: HIGH DURING CONFIGURATION
: LOW DURING COFIGURATION
: TEST DATA (WHEN BOUNDARY SCAN IS USED)
: BIDIRECTIONAL SIGNAL WITH AN OPTIONAL INTERNAL PULL-UP RESISTOR
: BIDIRECTIONAL SIGNAL (BEFORE AND DURING CONFIGURATION)
: INPUT AND/OR OUTPUT AFTER CONFIGURATION IS COMPLETED
XCS05XL-4VQ100C (XILINX)
IC