85
Pin No.
Pin Name
I/O
Function
DATO
XLAT
DSTB
VSS
VDD
BCKO
DACD
LRCO
GRST
XROF
SD0
SD1
SD2
SD3
VSS
SD4
SD5
SD6
SD7
VSS
VDD
XWAT
A0
A1
A2
A3
A4
A5
A6
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
INT
XCS
XWR
XRD
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
O
O
O
–
–
O
O
O
O
I
I
I
I
I
–
I
I
I
I
–
–
O
I
I
I
I
I
I
I
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
O
I
I
I
Serial data output from sub CPU to CD DSP
DAT0 latch signal. Latch at leading edge
DAT0 transfer clock
Ground
Power supply (+5V)
Bit clock (Connected to CXD3000 BCKI pin/pin 30)
Audio data output to DAC (Connected to CXD3000 PCMDI pin/pin 28)
LR clock output to DAC (Connected to CXD3000 LRCKI pin/pin 26)
Output for GRSCOR resyncronizing (Connected to CXD3000 SCSY pin/pin 68)
DSP RAM Overflow input (Connected to CXD3000/ROF pin/pin 45)
Test pin0
Test pin1
Test pin2
Test pin3
Ground
Test pin4
Test pin5
Test pin6
Test pin7
Ground
Power supply (+5V)
Wait signal for sub CPU buffer memory access
CXD1804R built-in register address bus0
CXD1804R built-in register address bus1
CXD1804R built-in register address bus2
CXD1804R built-in register address bus3
CXD1804R built-in register address bus4
CXD1804R built-in register address bus5
CXD1804R built-in register address bus6
Ground
Sub CPU data bus0
Sub CPU data bus1
Sub CPU data bus2
Sub CPU data bus3
Sub CPU data bus4
Sub CPU data bus5
Sub CPU data bus6
Sub CPU data bus7
Ground
Power supply (+5V)
Interruption to sub CPU
CXD1804R chip select signal
CXD1804R built-in register write signal
CXD1804R built-in register read signal
