8-2
8-2
A
B
C
D
E
F
G
H
1
2
3
4
5
BHA (2/2)
BHA (2/2)
BOARD CPU
D/A CONVERTER
BHA BLOCK (2/2)
8-2. BHA (2/2) BLOCK DIAGRAM
IC40
–5V REG
SI1
RST
SCLK2
SI2
P60/INTO
CS
SO
SI
CLK
1
5
6
IC2
EEP ROM
Q1
IC4(4/4)
IC4(2/4)
IC4(1/4)
RESET
IC4(3/4)
1
8
9
3
3
2
15
5
6
10
1
4
54
20
2
2
58
49
48
47
46
45
44
43
39
32
29
27
10
23
24
4
53
52
51
64
12
11
13
X1
8MHz
IC1
BOARD CPU
EE CS
SCLK1
S01
P50/CS16
X0
X1
P56/CS22
P26/CS14
P24/CS12
P21/CS09
P12
P06
P05
P04
P03
P02
P01
P00
P36
IC3
D/A CONVERTER
D1
17
19
2
3
7
8
12
13
16
15
LD
CLK
A02
1/2
1/2
1/2
1/2
1/2
1/2
1/2
A03
A04
A08
A09
A011
A012
SWITCH
IC10
12V REG
IC30
5V REG
IC20
+12V
–12V
+5V
–5V
+ 15V
+ 15V
– 15V
– 15V
+ 6V
+ 6V
– 6V
– 6V
A5
B5
A4
B4
A7
B7
A6
B6
–12V REG
PB LEVEL
PC LEVEL
PY LEVEL
V LEVEL
APT LEVEL
Y LEVEL
PR LEVEL
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
B27
MISO
33K
OE
GBR
INT-V
V-A
COMP A
COMP B
V-F
V-E
V-D
V-C
V-B
INT-YC
B26
SCLK
B28
MOSI
A28
CH-SLOT
A31