4-1(E)
SECTION 4
CIRCUIT OPERATIONS
1. Floating Type Input Buffer
The input buffer is composed of the Q101 and Q102 input
stages, Q103 and Q104 cascade-connected high gain ampli-
fiers, and Q106 emitter-follower. The frequency is expanded
by imposing a negative feed back on the output. The signals
input to the Q101 base can be switched to the ground of the
unit or ground of the signal source (floating) by setting SW1.
When set to floating, because the voltage between the Q101
base and emitter becomes stable, even if common mode noise
is present in the signal and ground line, the common mode
noise can be absorbed.
(This is the same for IN2, 3, 4, 5, and 6.)
2. Composite Signal Input Switching Circuit
When INPUT 1 is selected, only the V–A signal becomes
“L” (V–B, V–C are “H”), the IC101 SW turns ON (other
channel SWs are OFF), and the composite signal input to
INPUT 1 is output to TP100.
(This is the same for other channels.)
3. Component (33K)/GBR Signal Input
Switching Circuit
When INPUT 123 is selected, only the COMP A signal be-
comes “L” (COMP B is “H”), the IC101, IC201, and IC301
SWs turn ON (other channel SWs are OFF), and the compo-
nent signals input to INPUT 123 are output to TP400, TP500,
and TP600.
(This is the same for INPUT 456.)
4. Component (15K) Signal Input Switching
Circuit
When INPUT 123 is selected, only the COMP A signal be-
comes “L” (COMP B is “H”), and the IC101, IC201, and
IC301 SWs turn ON (other channel SWs are OFF). When
15K, since the 33K signal becomes “H”, the IC102, IC202,
and IC302 SW becomes ON, and the component signal in-
put is output to the aperture circuit in the next stage.
(This is the same for INPUT 456.)
5. YC Signal Input Switching Circuit
When INPUT 123 is selected, only the COMP A signal be-
comes “L” (COMP B is “H”), and the IC101, IC201, and
IC301 SWs turn ON (other channel SWs are OFF). When
the YC signal is input, as the 33K signal becomes “H” and
the INT–YC signal becomes “L”, the IC102 and IC202 SWs
turn ON, and the YC signal input is output to the circuit in
the next stage.
(This is the same for INPUT 456.)
6. Aperture Compensation Circuit
The aperture compensation signal is generated by two delay
lines (DL730, DL731). This compensation signal is level-
adjusted by IC700 and mixed with the Y signal. The aperture
compensation amount is controlled by the APT LEVEL volt-
age. The aperture circuit operates only on the 15K compo-
nent signal. To correspond to the delay time of the Y signal
passing through the aperture circuit, The B–Y and R–Y sig-
nals are also delayed in DL750 and DL770.
7. Level Adjustment Circuit, Output Circuit
The composite and YC signals are level-adjusted in the re-
spective gain control ICs (IC170, IC270, and IC370), passed
through the SW circuit (Q170 to Q174, Q270 to Q274, Q370
to Q374) using the transistor, and output to the signal line on
the mother board.
The component and GBR signals are level-adjusted in the
respective gain control ICs (IC451, IC551, and IC651), passed
through the SW circuit (Q470 to Q474, Q570 to Q574, Q670
to Q674, Q480 to Q484, Q580 to Q584, Q680 to Q684) us-
ing the transistor, and output to the Y, P
B
, and P
R
lines on the
mother board when 15K and to the 2Y, 2P
B
, and 2P
R
lines
when 33K.
8. Control Circuit
The CPU (IC1) carries out serial communication with the
system controller of the unit using the three signals MISO,
MOSI, and SCLK, and outputs control signals for selecting
switches, etc. according to the instructions from the system
controller. It also outputs adjustment data from the EEPROM
(IC2) and adjustment voltage from the D/A converter (IC3).
