C903
1228-1147 rev. 1
FUNCTIONAL OVERVIEW
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Technical Description
CODEC CCO Voltage Source
There is an internal voltage source CCO that provides the necessary drive current for
electret microphones. The voltage source is I²C programmable to 2.2 V or 2.4 V. The
source can be disabled during standby. A typical use case with a microphone connected to
MIC1 and the CCO is shown in picture below.
Earphone Amplifier
The earphone amplifiers (BEARP and BEARN) are mainly intended to be differentially
configured and drive a low impedance dynamic transducer (earpiece) but they can also be
single ended configured. The BEARP and BEARN amplifiers can be powered down by the
I2C. The amplifiers can exhibit high impedance to 1.4V or low impedance to ground when
powered-down. Fifty-one gains are available for BEARP and BEARN: from +15dB down to
–60dB in 1.5dB steps. When the BEARP and BEARN outputs are operating in differential
mode, an I²C selectable bit must invert one of the inputs.
Speaker Amplifier
The speaker amplifiers, SPKRP and SPKRN, are intended to drive a low impedance (8
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speaker in a differential mode or to be used as a stereo configured line output amplifier
supporting external high power amplifiers. The output buffer shall exhibit low impedance
to ground when powered-down and the current consumption shall be minimal. When the
SPKRP and SPKRN outputs are operating in differential mode, an I²C selectable bit must
invert one of the inputs.
Digital Baseband Controller (CPU)
N2010 (Kajsa)
This component is not replaceable on SL 4 because Baseband calibration is required.
The Digital Baseband Controller is divided in two subsystems: Access and Application
Access Subsystem
All modem functionality in the digital baseband controller resides in the Access subsystem.
This includes EDGE/GPRS/GSM interface, WCDMA interface, USB, IrDA, and other
peripheral modules. The control CPU is an ARM926 and a DSP is used for signal processing
and layer one control code.
The main communication between the blocks in the Access subsystem is done through the
Advanced High-performance Bus (AHB) matrix, which is a set of control buses connecting
the different parts together. A block called Syscon is responsible for distributing clocks and
resets to all parts of the Access subsystem. This block is under SW control. The Access
subsystem is connected to the Shared EMIF, an interface for communication with an
external SDRAM. The Shared EMIF is shared between the Access subsystem and the
Application subsystem.
Access Subsystem of the Digital Baseband Controller:
SEMC Troubleshooting Manual
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(129)
