SONIX SN8P27411 User Manual Download Page 124

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SN8P2740 Series

ADC, OP-amp, Comparator 8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 124

Version 2.0

Vdd

Vss

Vout

Vin-

Vin+

Vss

Vdd

1.011K ohm

RT1

50K ohm/

25 degree

100K ohm

R1 2.011K ohm

AIN1

Connect to JP23's P10O Pin

Connect to JP23's P12O Pin

Connect to JP23's P11O Pin

12. When SN8P2743

‟s OP-AMP function enable as the above figure. P12O (JP23) is OP-AMP‟s output. P11 (JP23) is

OP-

AMP‟s non-inverse. P10O (JP23) is OP-AMP‟s inverse.

13. If user wants to measure OP-AMP V+ / V- / Vo voltage as the above figure, the real OP-

AMP‟s inverse voltage is

OP3N (JP7). The real OP-

AMP‟s non-inverse voltage is OP3P (JP7). The real OP-AMP‟s output voltage is OP3O

(JP7).

14. Why OP-AMP connecting is different with measurement, because OP-AMP series connection with analog switch

internal resistor (Ron).

15. When CMP0 function enable. The CM0P/CM0N (JP17) will be external analog signal input pin. The P43O (JP23)

will be CMP0

‟s output result.

16. When CMP1 function enable. The CM1P/CM1N (JP16) will be external analog signal input pin. The P42O (JP23)

will be CMP1

‟s output result.

17. When CMP2 function enable. The CM2P/CM1N (JP8) will be external analog signal input pin. The P41O (JP23)

will be CMP2

‟s output result.

18. When user uses CMP0~CMP2

‟s CM0P/CM0N/CM1P/CM1N/CM2P/CM2N analog function, user must be

connecting to JP17/JP16/JP8. When user uses CMP0~CMP2

‟s CM0P/CM0N/CM0O/CM1P/CM1N/CM1O/CM2P/

CM2N/CM2O logic function, user must be connecting to JP23

‟s P02/P03/P43O/P16/P15/P42O/P14/P13/P41O.

19. When user uses TC0 special function (Pulse generator function and TC0 clock source is Fcpu.) in ICE emulation.

If user sets IDE breakpoint, the PWM plus generator output status will be unknown (Fcpu stop).

20. When user uses TC0 special function (Pulse generator function and TC0 clock source is Fhosc.) in ICE emulation.

If user sets IDE breakpoint, the PWM plus generator output will be finished (Fhosc still work). And the PWM pulse
generator output will be back to idle status.

21. When user uses CMP1 and CMP2

‟s de-bounce time control (CM1D3~CM1D0, CM2D3~CM2D0 and clock source

is Fcpu) in ICE emulation. If user sets IDE breakpoint, the CM0O output will be effected (Fcpu stop)

22. When user uses CMP0

‟s de-bounce time control (CM0D3~CM0D0 and clock source is Fhosc) in ICE emulation.

If user sets IDE breakpoint, the CM0O output will be not effected (Fhosc still work).

Summary of Contents for SN8P27411

Page 1: ...ed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which th...

Page 2: ...ay 2011 1 Version update 2 Modify DEVELOPMENT TOOL description 3 Modify Chapter 16 3 CHARACTERISTIC GRAPHS VER 1 1 May 2011 1 Modify Chapter 10 4 COMPARATOR MODE REGISTER CMDB0 register bit3 CM1D3 CM0...

Page 3: ...ISTERS 30 2 2 7 R REGISTER 30 2 3 ADDRESSING MODE 31 2 3 1 IMMEDIATE ADDRESSING MODE 31 2 3 2 DIRECTLY ADDRESSING MODE 31 2 3 3 INDIRECTLY ADDRESSING MODE 31 2 4 STACK OPERATION 32 2 4 1 OVERVIEW 32 2...

Page 4: ...INTERRUPT OPERATION 65 6 10 COMPARATOR INTERRUPT OPERATION CMP0 CMP2 66 6 11 MULTI INTERRUPT OPERATION 67 7 7 7 I O PORT 68 7 1 OVERVIEW 68 7 2 I O PORT MODE 69 7 3 I O PULL UP REGISTER 70 7 4 I O POR...

Page 5: ...PTION AND NOTIC 111 13 4 1 ADC SIGNAL FORMAT 111 13 4 2 ADC CONVERTING TIME 111 13 4 3 ADC PIN CONFIGURATION 112 13 5 ADC OPERATION EXAMLPE 113 13 6 ADC APPLICATION CIRCUIT 115 1 1 14 4 4 RAIL TO RAIL...

Page 6: ...rnal interrupt INT0 On chip watchdog timer and clock source is Internal low clock RC type 16KHz 3V 32KHz I O pin configuration 5V Bi directional P0 P1 P4 Wakeup P0 P1 level change 4 system clocks Pull...

Page 7: ...3 PIN ASSIGNMENT SN8P2743K SKDIP 24 pin SN8P2743S SOP 24 pin VSS 1 U 24 VDD XIN P0 6 2 23 P4 7 AIN7 XOUT P0 5 BZ 3 22 P4 6 AIN6 RST VPP P0 4 4 21 P4 5 AIN5 P0 0 INT0 5 20 P4 4 AIN4 P0 1 PWM0 6 19 P4...

Page 8: ...n Schmitt trigger structure as input mode Built in pull up resisters Level change wake up XOUT P0 5 BZ I O XOUT Oscillator output pin while external crystal enable P0 5 Bi direction pin Schmitt trigge...

Page 9: ...mode Built in pull up resisters AIN1 ADC analog input pin CM2O The output pin of comparator P4 2 AIN2 CM1O I O P4 2 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters...

Page 10: ...8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 10 Version 2 0 Pull Up Resistor Output Latch Pin PnUR PnM I O Input Bus I O Output Bus PnM P0 1 Open drain shared pin output only I O Pin Open Drain...

Page 11: ...us I O Output Bus PnM OP amp shared pins structure Pin OPnEN Op amp Terminal Pull Up Resistor Output Latch PnUR PnM I O Input Bus I O Output Bus PnM Comparator shared pins structure Comparator Negativ...

Page 12: ...0008H Interrupt vector User interrupt vector 0009H General purpose area User program 000FH 0010H 0011H 0FFCH End of user program 0FFDH Reserved 0FFEH 0FFFH The ROM includes Reset vector Interrupt vec...

Page 13: ...r on reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset sta...

Page 14: ...tor The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and o...

Page 15: ...of user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI E...

Page 16: ...BLE1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To...

Page 17: ...To define a word 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register b...

Page 18: ...e head of the ROM boundary B0ADD PCL A PCL PCL ACC PCH 1 when PCL overflow occurs JMP A0POINT ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC...

Page 19: ...er of the jump table listing is five 0X00FD JMP A0POINT ACC 0 jump to A0POINT 0X00FE JMP A1POINT ACC 1 jump to A1POINT 0X00FF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP A3POINT ACC 3 jump to A3POINT...

Page 20: ...end address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end o...

Page 21: ...Y Z Working YZ and ROM addressing register R Working register and ROM look up data buffer PFLAG Special flag register CMDB0 Comparator output de bounce control register 0 CMDB1 Comparator output de bo...

Page 22: ...CPUM0 CLKMD STPHX R W OSCM 0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC1...

Page 23: ...W STK0L 0FFH S0PC11 S0PC10 S0PC9 S0PC8 R W STK0H Note 1 To avoid system error make sure to put all the 0 and 1 as it indicates in the above table 2 All of register names had been declared in SN8ASM a...

Page 24: ...n t be access by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Wr...

Page 25: ...LVD 1 1 Reset by external Reset Pin Bit 5 LVD36 LVD 3 6V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 3 6V 1 Active VDD 3 6V Bit 4 LVD24 LVD 2 4V operating flag and only sup...

Page 26: ...11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are n...

Page 27: ...INCS BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results...

Page 28: ...value by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automa...

Page 29: ...Bit 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example If want to read a data from RAM address 20H of bank_0 it can use ind...

Page 30: ...Y 00H To set RAM bank 0 for Y register B0MOV Z 25H To set location 25H for Z register B0MOV A YZ To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data B0MOV Y 0 Y...

Page 31: ...out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a c...

Page 32: ...L instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program co...

Page 33: ...t service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit...

Page 34: ...1H STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond...

Page 35: ...stops in power down mode and green mode Disable Disable Watchdog function Reset_Pin Reset Enable External reset pin P04 Enable P0 4 input only without pull up resister Security Enable Enable ROM code...

Page 36: ...Condition Description 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin det...

Page 37: ...s and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following Watchdog timer status System checks watchdog timer overflow status If...

Page 38: ...ry heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power...

Page 39: ...flags indicate VDD voltage level For low battery detect application only checking LVD24 LVD36 status to be battery status This is a cheap and easy solution 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit...

Page 40: ...ously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown...

Page 41: ...gh level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator o...

Page 42: ...et circuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Elect...

Page 43: ...7V If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is...

Page 44: ...lock diagram Fhosc Fcpu Fhosc 4 Fhosc 16 Flosc Fcpu Flosc 4 CPUM 1 0 XIN XOUT STPHX HOSC Fcpu Code Option Fosc Fosc CLKMD Fcpu HOSC High_Clk code option Fhosc External high speed clock Internal high s...

Page 45: ...amic The oscillator bandwidth is 10MHz 16MHz 4M X tal The system high speed clock source is external high speed crystal resonator The oscillator bandwidth is 1MHz 10MHz 4 3 2 INTERNAL HIGH SPEED OSCIL...

Page 46: ...00 30 00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD bit of OSCM regist...

Page 47: ...reserved STPHX bit controls internal high speed RC type oscillator and external oscillator operations When STPHX 0 the external oscillator or internal high speed RC type oscillator active When STPHX 1...

Page 48: ...8 Fhosc Power on reset LVD reset watchdog reset external reset pin active 64ms Fhosc 32KHz 512us Fhosc 4MHz 128us Fhosc 16MHz Oscillator warm up time of power down mode wake up condition 2048 Fhosc Cr...

Page 49: ...erflow Power Down Mode Wake up Timing Wake up Pin Rising Edge Oscillator Fcpu Instruction Cycle Tosp Tost Wake up Pin Falling Edge System inserts into power down mode Edge trigger system wake up Green...

Page 50: ...The start up time is depended on oscillator s material factory and architecture Normally the low speed oscillator s start up time is lower than high speed oscillator The RC type oscillator s start up...

Page 51: ...ter is overflow Wake up condition P0 P1 input status is level changing Reset Control Block One of reset trigger sources actives One of reset trigger sources actives One of reset trigger sources active...

Page 52: ...is executed and full functions are controllable The system rate is low speed Flosc 4 The internal low speed RC type oscillator actives and the high speed oscillator is controlled by STPHX 1 In slow mo...

Page 53: ...the system inserts into green mode After system wake up from green mode the CPUM1 bit is disabled zero status automatically The program stops executing and full functions are disabled Only the timer...

Page 54: ...to power down sleep mode SleepMode Declare SleepMode macro directly Example Switch normal mode to slow mode SlowMode Declare SlowMode macro directly Example Switch slow mode to normal mode The externa...

Page 55: ...The system issues external interrupt request and executes interrupt service routine 5 7 2 WAKEUP TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up fro...

Page 56: ...level changing When wake up pin occurs rising edge or falling edge the system is waked up by the trigger edge The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the P...

Page 57: ...upt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next inte...

Page 58: ...d Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 0 P00IEN External P0 0 interrupt INT0 control bit 0 Disable INT0 interrupt function 1 Enable INT0 interrupt function Bit 1 CM0IEN Comp...

Page 59: ...2IRQ CM1IRQ CM0IRQ P00IRQ Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 0 P00IRQ External P0 0 interrupt INT0 request flag 0 None INT0 interrupt request 1 INT0 interrupt request...

Page 60: ...of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 S...

Page 61: ...wo instructions save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH...

Page 62: ...from power down mode the wake up source is external interrupt source P0 0 and the trigger edge direction matches interrupt edge configuration the trigger edge will be latched and the system executes i...

Page 63: ...pt request setup Fcpu 4MHz 4 B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 64H Set T0C initial value 64H B0MOV T0C A Set T0...

Page 64: ...n Example TC0 interrupt request setup Fcpu 16MHz 16 B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 64H Set TC0C initia...

Page 65: ...ation under multi interrupt situation Example ADC interrupt request setup B0BCLR FADCIEN Disable ADC interrupt service MOV A 10110000B B0MOV ADM A Enable P4 0 ADC input and ADC function MOV A 00000000...

Page 66: ...om low to high as CM0P CM0N 09DH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CM1M CM1EN CM1OEN CM1OUT CM1SF CM1G CM1RS2 CM1RS1 CM1RS0 Read Write R W R W R W R W R W R W R W R W After Reset 0 0 0 0...

Page 67: ...hings need to be taking care of One is to set the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bi...

Page 68: ...AC CM0EN 1 P0 3 I O CM0N AC CM0EN 1 P0 4 I RST DC Reset_Pin code option Reset VPP HV OTP Programming P0 5 I O XOUT AC High_CLK code option 32K 4M 12M BZ DC BZEN 1 P0 6 I O XIN AC High_CLK code option...

Page 69: ...5M P14M P13M P12M P11M P10M Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4M P47M P46M P45M P44M P43M P42M P41M P40M Read Write...

Page 70: ...abled 0E0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0UR P06R P05R P03R P02R P00R Read Write W W W W W After reset 0 0 0 0 0 0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P16R P15R...

Page 71: ...44 P43 P42 P41 P40 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Note 1 The P04 keeps 1 when external reset enable by code option 2 If set one bit of P0 register P0 n bit reco...

Page 72: ...iguration control bits 0 P4 n can be an analog input ADC input or digital I O pins 1 P4 n is pure analog input can t be a digital I O pin Note When Port 4 n is general I O port not ADC channel P4CON n...

Page 73: ...1 Set P4 1 buffer as 0 Enable P4 1 output mode B0BSET P4M 1 Set P4 1 as input mode P4 0 is shared with general purpose I O ADC input AIN0 and ADC external high reference voltage input AVREFH flag of A...

Page 74: ...clear it to disable external ADC high reference input AVREFH 0 execute next routine Check GCHS and CHS 2 0 status B0BCLR FGCHS If CHS 2 0 point to P4 0 CHS 2 0 000B set GCHS 0 If CHS 2 0 don t point t...

Page 75: ...and slow mode In power down mode and green mode the watchdog timer stops Always_On Enable watchdog timer function The watchdog timer actives and not stop in power down mode and green mode In high noi...

Page 76: ...l Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To cle...

Page 77: ...inary Up Counting Counter T0IRQ Interrupt Flag T0 timer overflow Load T0C Value by Program 8 2 2 T0 TIMER OPERATION T0 timer is controlled by T0ENB bit When T0ENB 0 T0 timer stops When T0ENB 1 T0 time...

Page 78: ...it 6 4 T0RATE 2 0 T0 timer clock source select bits 000 Fcpu 256 001 Fcpu 128 010 Fcpu 64 011 Fcpu 32 100 Fcpu 16 101 Fcpu 8 110 Fcpu 4 111 Fcpu 2 Bit 7 T0ENB T0 counter control bit 0 Disable T0 timer...

Page 79: ...XPLAME T0 TIMER CONFIGURATION Reset T0 timer CLR T0M Clear T0M register Set T0 clock source and T0 rate MOV A 0nnn0000b B0MOV T0M A Set T0C register for T0 Interval time MOV A value B0MOV T0C A Clear...

Page 80: ...f the TC0 timer are as following 8 bit programmable up counting timer Generate time out at specific time intervals based on the selected clock frequency Interrupt function TC0 timer function supports...

Page 81: ...ne after TC0 overflow occurrence Clear TC0IRQ by program is necessary in interrupt procedure TC0 timer can works in normal mode slow mode and green mode But in green mode TC0 keep counting set TC0IRQ...

Page 82: ...ecided by TC0R TC0R range is from 0x00 0xFF If TC0R 0x00 PWM s resolution is 1 256 If TC0R 0x80 PWM s resolution is 1 128 TC0D controls the high pulse width of PWM for PWM s duty When TC0C TC0D PWM ou...

Page 83: ...0OUT bit is cleared as TC0 counter overflow To output next pulse is to set PWM0OUT bit by program again TC0 Rate Fhosc 2 8MHz Fhosc 16MHz TC0C TC0R 0x00 0x01 0xFE 0xFF Pulse Width ns 31875 31750 125 0...

Page 84: ...ge occurs TC0 starts to count If TC0 overflows TC0 stops counting TC0IRQ is issued and TC0C reloads new value from TC0R TC0C Counter Initial Value TC0R M TC0ENB TC0 overflows TC0C reloads from TC0R TC...

Page 85: ...high idle status Bit 3 TC0CKS TC0 clock source select bit 0 TC0 clock source is internal system clock Fcpu 1 TC0 clock source is high clock source Fhosc Bit 6 4 TC0RATE 2 0 TC0 timer clock source sel...

Page 86: ...ial value 256 TC0 interrupt interval time TC0 clock rate Example To calculation TC0C and TC0R value to obtain 10ms TC0 interval time TC0 clock source is Fcpu 16MHz 16 1MHz Select TC0RATE 000 Fcpu 128...

Page 87: ...er and interrupt function B0BSET FTC0IEN Enable TC0 interrupt function B0BSET FTC0ENB Enable TC0 timer TC0 PWM CONFIGURATION Reset TC0 timer CLR TC0M Clear TC0M register Set TC0 rate MOV A 0nnn0000b B...

Page 88: ...source is Fhosc Set TC0C and TC0R register for pulse width MOV A value1 TC0C must be equal to TC0R B0MOV TC0C A B0MOV TC0R A Set pulse output phase B0BCLR FTC0DIR High pulse and low idle status or B0...

Page 89: ...and negative input terminal Interrupt function Comparator 0 supports interrupt function When comparator 0 output edge direction equals to edge selection the CM0IRQ actives and the system points progra...

Page 90: ...lt The event condition is controlled by register and includes rising edge CM0OUT changes from low to high and falling edge CM0OUT changes from high to low controlled by CM0G bit When CM0G 0 the compar...

Page 91: ...6 Fhosc 7 Fhosc 8 Fhosc 9 Fhosc 10 Fhosc 11 Fhosc 12 Fhosc 13 Fhosc 14 Fhosc 15 Fhosc controlled by CM0D 3 0 bits CM0D 3 0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b No 1 Fhosc 2 Fhosc 3 Fhosc 4...

Page 92: ...r interrupt function actives More detail operation is referred to TC0 pulse generator contents CM0P CM0N CM0OUT without delay TC0 Pulse Generator Idle High Falling Edge Trigger TC0 Pulse Generator Idl...

Page 93: ...nd isolate GPIO function Bit 7 CM0EN Comparator 0 control bit 0 Disable Comparator pins are GPIO mode 1 Enable CM0N and CM0P pins are comparator mode CM0O is controlled by CM0OEN bit 09AH Bit 7 Bit 6...

Page 94: ...ode Set Comparator 0 output pin B0BCLR FCM0OEN Disable comparator 0 output pin or B0BSET FCM0OEN Enable comparator 0 output pin Set Comparator 0 interrupt trigger edge B0BCLR FCM0G Falling edge or B0B...

Page 95: ...e two tensions of positive input terminal and negative input terminal Interrupt function Comparator 1 supports interrupt function When comparator 1 output edge direction equals to edge selection the C...

Page 96: ...CM1P GPIO Comparator Comparator Internal Logic Internal Reference Voltage CM1N CM1O GPIO CM1P Comparator Comparator Internal Logic CM1N CM1O GPIO CM1P GPIO Comparator Comparator Internal Logic Interna...

Page 97: ...nal s voltage and negative terminal s voltage and then output result to output pin When V V comparator outputs high status When V V comparator outputs low status Comparator output terminal builds in d...

Page 98: ...ithout delay TC0 Pulse Generator Idle High Falling Edge Trigger TC0PO bit CM1SF bit Correct pulse width Change to idle status by falling edge Disable by falling edge Disable by falling edge Enable by...

Page 99: ...Comparator output status is from low to high as CM1P CM1N Bit 4 CM1SF Comparator 1 special mode control bit 0 Disable Comparator 1 is normal comparator function 1 Enable Comparator 1 output edge trig...

Page 100: ...ME COMPARATOR 1 CONFIGURATION Reset Comparator 1 CLR CM1M Clear CM1M register Set Comparator 1 positive terminal MOV A 00000nnnb Set CM1RS 2 0 for comparator positive terminal B0MOV CM1M A Set Compara...

Page 101: ...tensions of positive input terminal and negative input terminal Interrupt function Comparator 2 supports interrupt function When comparator 2 output edge direction equals to edge selection the CM2IRQ...

Page 102: ...CM2P GPIO Comparator Comparator Internal Logic Internal Reference Voltage CM2N CM2O GPIO CM2P Comparator Comparator Internal Logic CM2N CM2O GPIO CM2P GPIO Comparator Comparator Internal Logic Intern...

Page 103: ...nal s voltage and negative terminal s voltage and then output result to output pin When V V comparator outputs high status When V V comparator outputs low status Comparator output terminal builds in d...

Page 104: ...cycle If the comparator output status exchanges to expand TC0 pulse width through increasing TC0R register by program CM0P CM0N Normal TC0 Pulse Generator CM2P CM2N TC0 Pulse Generator Comparator Tri...

Page 105: ...2N 1 Rising edge trigger Comparator output status is from low to high as CM2P CM2N Bit 4 CM2SF Comparator 2 special mode control bit 0 Disable Comparator 2 is normal comparator function 1 Enable Compa...

Page 106: ...OPERATION EXPLAME COMPARATOR 2 CONFIGURATION Reset Comparator 2 CLR CM2M Clear CM2M register Set Comparator 2 positive terminal MOV A 00000nnnb Set CM2RS 2 0 for comparator positive terminal B0MOV CM2...

Page 107: ...ate 1 0 Buzzer Rate Division Buzzer Rate Fcpu 1MHz Fcpu 2MHz Fcpu 4MHz 00 Fcpu 256 4KHz 8KHz 16KHz 01 Fcpu 512 2KHz 4KHz 8KHz 10 Fcpu 1024 1KHz 2KHz 4KHz 11 Fcpu 2048 0 5KHz 1KHz 2KHz The buzzer targe...

Page 108: ...P4CON register to set pure analog input pin It is necessary to set P4 as input mode without pull up resistor by program After setup ADENB and ADS bits the ADC starts to convert analog signal to digita...

Page 109: ...erting stops 1 Start to execute ADC converting Bit 5 EOC ADC status bit 0 ADC progressing 1 End of converting and reset ADS bit Bit 4 GCHS ADC global channel select bit 0 Disable AIN channel 1 Enable...

Page 110: ...it 1 Bit 0 ADR ADCKS1 ADLEN ADCKS0 ADB3 ADB2 ADB1 ADB0 Read Write R W R W R W R R R R After reset 0 0 0 Bit 3 0 ADB 3 0 12 bit low nibble ADC data buffer The AIN input voltage v s ADB output data AIN...

Page 111: ...me duration is depend on ADC resolution and ADC clock rate 12 bit ADC s converting time is 1 ADC clock 4 16 sec and the 8 bit ADC converting time is 1 ADC clock 4 12 sec ADC clock source is Fcpu and i...

Page 112: ...resistor The GPIO mode of ADC external high reference voltage input pin must be set as input mode The internal pull up resistor of ADC external high reference voltage input pin must be disabled ADC in...

Page 113: ...Execute ADC 100us warm up time delay loop CALL 100usDLY 100us delay loop Select ADC input channel MOV A value Set ADCHS 2 0 for ADC input channel selection OR ADM A Enable ADC input channel B0BSET FG...

Page 114: ...ADC Interrupt enable mode ORG 8 Interrupt vector INT_SR Interrupt service routine PUSH B0BTS1 FADCIRQ Check ADC interrupt flag JMP EXIT_INT ADCIRQ 0 Not ADC interrupt request B0MOV A ADB ADCIRQ 1 End...

Page 115: ...the side of the ADC input pin as possible Don t connect the capacitor s ground pin to ground plain directly and must be through VSS pin The capacitor can reduce the power noise effective coupled with...

Page 116: ...with GPIO controlled by OPEN bit When OPEN 0 OP AMP pins are GPIO mode When OPEN 1 GPIO pins switch to OP AMP and isolate GPIO path OP pins selection table is as following OP No OPEN OP Positive Pin...

Page 117: ...I A A and I 1 G OR A M A A or M 1 I OR M A M A or M 1 N C OR A I A A or I 1 XOR A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4...

Page 118: ...in Vdd 2 uA I O port pull up resistor Rup Vin Vss Vdd 3V 100 200 300 K Vin Vss Vdd 5V 50 100 150 I O output source current IoH Vop Vdd 0 5V 8 mA sink current IoL Vop Vss 0 5V 8 INTn trigger pulse widt...

Page 119: ...ss 130 uA Unit Gain Buffer Vdd 5V OPP Vss 150 uA Common Mode Input Voltage Range Vcmr Vdd 5 0V Vss 0 3 Vdd 0 3 V Input Offset Voltage Vos Vcm Vss 3 3 mV Power Supply Rejection Ratio PSRR Vcm Vss 50 70...

Page 120: ...ARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and...

Page 121: ...al chip provides an EV KIT to achieve PWM and the analog functions emulations For SN8P2743 42 ICE emulation the EV Kit includes OP Comparator PWM ADC LVD2 4V 3 6V and switch circuits EV2740 KIT PCB Ou...

Page 122: ...EFH P1 5 CM1N 8 13 P1 0 OPN P1 4 CM2P 9 12 P1 1 OPP P1 3 CM2N 10 11 P1 2 OPO C32 C39 Connect 0 1uF capacitors to AIN0 AIN7 input which are ADC channel 0 7 bypass capacitors C40 Connect 0 1uF capacitor...

Page 123: ...8ICE2K Plus power switch If LED D1 is not light that means user contact to SONIX s agent right now 6 If user program select chip SN8P2743 JP24 open Or user program select chip SN8P2742 JP24 short Jump...

Page 124: ...When CMP2 function enable The CM2P CM1N JP8 will be external analog signal input pin The P41O JP23 will be CMP2 s output result 18 When user uses CMP0 CMP2 s CM0P CM0N CM1P CM1N CM2P CM2N analog funct...

Page 125: ...46 DIP46 PGM OTPCLK 5 6 OE ShiftDat DIP 4 4 45 DIP45 D1 7 8 D0 DIP 5 5 44 DIP44 D3 9 10 D2 DIP 6 6 43 DIP43 D5 11 12 D4 DIP 7 7 42 DIP42 D7 13 14 D6 DIP 8 8 41 DIP41 VDD 15 16 VPP DIP 9 9 40 DIP40 HL...

Page 126: ...P4 0 28 14 P4 0 28 4 CE 5 PGM 20 P4 4 32 18 P4 4 32 6 OE 17 P4 1 29 15 P4 1 29 7 D1 8 D0 9 D3 10 D2 11 D5 12 D4 13 D7 14 D6 15 VDD 16 VPP 4 RST 16 4 RST 18 17 HLS 18 RST 19 20 ALSB PDB 3 XOUT P0 5 15...

Page 127: ...roduction line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 19 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bi...

Page 128: ...2743 SOP 40 85 Green Package SN8P27411PG OTP 2743 DIP 20 70 Green Package SN8P27411SG OTP 2743 SOP 20 70 Green Package SN8P27411PDG OTP 2743 DIP 40 85 Green Package SN8P27411SDG OTP 2743 SOP 40 85 Gre...

Page 129: ...o Controller SONiX TECHNOLOGY CO LTD Page 129 Version 2 0 19 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A October B November C December SONiX Internal Use Day 1 01 2 0...

Page 130: ...ORMATION 20 1 SK DIP 24 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 1 230 1 250 1 280 31 242 31 750 32 512 E 0 300 BSC 7 620 BSC E...

Page 131: ...age 131 Version 2 0 20 2 SOP 24 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 069 1 753 A1 0 004 0 010 0 102 0 254 D 0 612 0 618 0 624 15 545 15 697 15 850 E 0 292 0 296 0 299 7 417 7 518 7 595 H 0...

Page 132: ...3 P DIP 20 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 980 1 030 1 060 24 892 26 162 26 924 E 0 300 7 620 E1 0 245 0 250 0 255...

Page 133: ...0 20 4 SOP 20 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 496 0 502 0 508 12 598 12 751 12 903 E 0 291 0 295 0 299 7 39...

Page 134: ...P DIP 16 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 735 0 775 0 775 18 669 19 177 19 685 E 0 300BSC 7 620BSC E1 0 245 0 250 0 2...

Page 135: ...ersion 2 0 20 6 SOP 16 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 069 1 75 A1 0 004 0 010 0 10 0 25 A2 0 049 1 25 b 0 012 0 020 0 31 0 51 c 0 004 0 010 0 10 0 25 D 9 90BSC 9 90BSC E 6 00BSC 6 00B...

Page 136: ...tes and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such...

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