SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 66
Version 2.0
6.10 COMPARATOR INTERRUPT OPERATION (CMP0~CMP2)
Sonix provides 3 sets comparator with interrupt function in the micro-controller. The comparator interrupt trigger edge
direction is controlled by comparator register. CM0G of CM0M is control comparator 0 interrupt trigger edge direction.
CM1G of CM1M is control comparator 1 interrupt trigger edge direction. CM2G of CM2M is control comparator 2
interrupt trigger edge direction. When the comparator output status transition occurs, the comparator interrupt request
flag will be set to
“1” no matter the comparator interrupt control bit status. The comparator interrupt flag doesn‟t active
only when comparator control bit is disabled. When comparator interrupt control bit is enabled and comparator interrupt
edge trigger is occurring, the program counter will jump to the interrupt vector (ORG 8) and execute interrupt service
routine.
09CH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM0M
CM0EN
CM0OEN
CM0OUT
CM0SF
CM0G
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R/W
-
-
-
After Reset
0
0
0
0
0
-
-
-
Bit 3
CM0G:
Comparator 0 interrupt trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM0P < CM0N.
1 = Rising edge trigger. Comparator output status is from low to high as CM0P > CM0N.
09DH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM1M
CM1EN
CM1OEN
CM1OUT
CM1SF
CM1G
CM1RS2
CM1RS1
CM1RS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After Reset
0
0
0
0
0
0
0
0
Bit 3
CM1G:
Comparator 1 output trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM1P < CM1N.
1 = Rising edge trigger. Comparator output status is from low to high as CM1P > CM1N.
09EH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM2M
CM2EN
CM2OEN
CM2OUT
CM2SF
CM2G
CM2RS2
CM2RS1
CM2RS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After Reset
0
0
0
0
0
0
0
0
Bit 3
CM2G:
Comparator 2 output trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM2P < CM2N.
1 = Rising edge trigger. Comparator output status is from low to high as CM2P > CM2N.
Example: Setup comparator 0 interrupt request and falling edge trigger.
MOV
A, #00H
B0MOV
CM0M, A
; Set comparator 0 interrupt trigger as bi-direction edge.
B0BSET
FCM0IEN
; Enable comparator 0 interrupt service
B0BCLR
FCM0IRQ
; Clear comparator 0 interrupt request flag
B0BSET
FCM0EN
; Enable comparator 0.
B0BSET
FGIE
; Enable GIE
Example: Comparator 0 interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FCM0IRQ
; Check CM0IRQ
JMP
EXIT_INT
; CM0IRQ = 0, exit interrupt vector
B0BCLR
FCM0IRQ
; Reset CM0IRQ
…
; Comparator 0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
