6.2 Programming the Clock Path
Given a valid VCO frequency for the M unique frequencies, segregate the N-M equal frequencies into known output banks. When
arranging outputs, care must be taken to minimize crosstalk (without violating the constraints imposed from the grouping of output
frequencies into the VDDO “banks”). Whenever several high frequencies, fast rise time, large amplitude signals are all close to one
another, the laws of physics dictate that there will be some amount of crosstalk. The jitter of the Si5357 is low and therefore crosstalk
can become a significant portion of the final measured output jitter. Some of the source of the crosstalk will be the Si5357 and some will
be introduced by the PCB. For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can
be minimized by modifying the arrangements of different output clocks
A few guidelines are:
1. Avoid adjacent frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock. If the jitter
integration bandwidth goes up to 20 MHz, then keep adjacent frequencies at least 20 MHz apart.
2. Adjacent frequency values that are integer multiples of one another are okay and these outputs should be grouped accordingly.
3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. If some outputs have tight
jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible
to crosstalk. These guidelines typically only need to be followed by those applications that wish to achieve the highest possible
levels of jitter performance. Because CMOS outputs have large pk-pk swings and do not present a balanced load to the VDDO
supplies, Si5357 will have larger jitter than the Si5332.
An output multiplexer (output mux) or crosspoint mux needs to be programmed such that each frequency Fx is set to the correct
O-divider,N-divider, or input clock (in the case of buffering). Each output, Fx, has this common divider or input clock reference that
needs to be set. The multiplier setting that routes the correct divider/clock source to the correct group is shown in the following table.
Table 6.5. Output Mux (Crosspoint Mux) Settings
Register field
Description
Omuxx_y_sel0
Selects output mux clock for output clocks OUTx, OUTy:
0 = PLL reference clock before pre-scaler
1 = PLL reference clock after pre-scaler
2 = Clock from CLKIN_2
omuxx_y_sel1
Selects output mux clock for output clocks OUTx, OUTy:
clock source:
0 = HSDIV0
1 = HSDIV1
2 = HSDIV2
3 = HSDIV3
4 = HSDIV4
5 = ID0
6 = ID1
7 = Clock from omuxx_y_sel0
Si5357 Reference Manual • Programming the Volatile Memory
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021
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