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2. Power Supply Sequencing

The  Si5357  VDD_core  voltages  are  VDD_DIG,  VDD_XTAL  and  VDDA.  These  3  VDD_core  pins  must  all  use  the  *same*  voltage.
Power supply sequencing between VDD_core and any VDDOx pin is allowed in any order. However, to minimize the “bring up” time,
it  is  recommended  that  VDD_core  is  powered  up  first,  this  ensures  that  the  NVM  download  is  completed  first.  The  register  bit  field
“VDD_XTAL_OK”  is  set  to  indicate  input  buffer(s)  and  crystal  oscillator  are  powered  up.  Once  the  appropriate  VDDOx  supplies  are
powered-up,  the  VDDO_OK  register  field  will  indicate  output  driver  bank  supply  voltage  status.  These  status  registers  are  available
to  provide  an  indication  of  general  device  status  and  presence  of  output  driver  voltages.  The  figure  below  shows  the  Si5332  device
power-up  sequencing  and  expected  device  behavior.  Note  that  a  blank  (unconfigured)  part  will  stop  and  wait  to  be  configured  with
outputs disabled.

Power supplies for VDDA,

VDD_DIG, VDD_XTAL

stable

Time (system time delay)

for NVM download

Is this a blank part?

Yes

No

Time (system time delay) for

Oscillator startup/ Time

(system time delay) for input

clock availability

Time (system time delay)

for PLL lock

Outputs available and

stable

Program Si5332 volatile

memory with a frequency

plan

Figure 2.1. Power Supply Sequencing for Si5357

Si5357 Reference Manual • Power Supply Sequencing

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021

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Summary of Contents for Si5357

Page 1: ...0 170 MHz 10 170 MHz 10 170 MHz 10 170 MHz 10 170 MHz 1 63 10 50 MHz 10 170 MHz 10 170 MHz 10 30 MHz VDD_XTAL VDDA VDDOA VDDOB VDDOC VDDOD VDDOE XA CLKIN_1 XB CLKIN_2 nCLKIN_2 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 KEY FEATURES Any Frequency 12 output programmable clock generator Offered in 32 pin QFN package Multisynth technology enables any frequency synthesis on any outpu...

Page 2: ...mming the Clock Path 17 6 3 Programming the Output Clock Frequency 18 6 4 Programming the Output Clock Format 19 6 5 Programming for Frequency Select Operations 20 6 6 Programming for Spread Spectrum 21 7 Recommended Schematic and Layout Practices 23 8 Register Map 24 Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 2 Rev 0 2 Skyworks Proprietary...

Page 3: ...ons and controls of the Si5357 are mainly handled through I2C Any GPI pin can be programmed to be clock input select frequency select spread enable output enable resetb and I2C address select To enable in system programming a power up mode is available through OTP which powers up the chip in an OTP defined default mode but with no outputs enabled This allows a microcontroller to first write a user...

Page 4: ... status and presence of output driver voltages The figure below shows the Si5332 device power up sequencing and expected device behavior Note that a blank unconfigured part will stop and wait to be configured with outputs disabled Power supplies for VDDA VDD_DIG VDD_XTAL stable Time system time delay for NVM download Is this a blank part Yes No Time system time delay for Oscillator startup Time sy...

Page 5: ...rt ONLY external clock inputs The GPI pins can be set to select the active input clock for the PLL or the user can set the active input via register writes Si5357 Reference Manual Input Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 5 Rev 0 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without ...

Page 6: ...between Figure 3 1 Termination for Connecting a Crystal to XA XB Pins in Crystal Mode on page 6 and Figure 3 2 Termination for Connecting an External Clock Input to XA XB Pins on page 6 are 1 Termination for a reference clock input on XA XB must be external to Si5357 2 The choice to enable the internal crystal oscillator or internal capacitance loads or to disable their use is controlled by progra...

Page 7: ...e 3 4 Termination for AC Coupling an External LVDS Clock Input to CLKIN_x CLKIN_x Pins CLKIN_x CLKIN_x Clock IC External oscillator clock source Input buffer Add any output termination needed by the clock source Figure 3 5 Termination for DC Coupling a Differential Clock Input to CLKIN_x CLKIN_x Pins Si5357 Reference Manual Input Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sa...

Page 8: ...a Single Ended Clock Input to CLKIN_x CLKIN_x Pins CLKIN_x CLKIN_x Clock IC External oscillator clock source Input buffer 0 1 µF The swing of the clock source can be any value between 1V 4V 0 1 µF Figure 3 8 Termination for AC Coupling a Single Ended Clock Input to CLKIN_x CLKIN_x Pins Si5357 Reference Manual Input Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc...

Page 9: ... 4 NDK 30ppm 8pf 50 Ω NX5032GA 25 000000MHZ LN CD 1 30ppm 8pf 70 Ω NX5032GA 27M STD CSK 4 30ppm 8pf 50 Ω NX5032GA 27 000000MHZ LN CD 1 30ppm 8pf 70 Ω 7A 25 000MAAE TXC 30ppm 12pf 50 Ω 7A 25 000MAAJ 30ppm 18pf 50 Ω 7A 27 000MAAE 30ppm 12pf 50 Ω 7A 27 000MAAJ 30ppm 18pf 50 Ω When a crystal input is used it is strongly recommended that the internal load capacitances CL in table 1 are enabled CL is th...

Page 10: ...quency select for outputs derived from O1 FS_O2 Frequency select for outputs derived from O2 FS_O3 Frequency select for outputs derived from O3 FS_O4 Frequency select for outputs derived from O4 CLKIN_SEL0 Input clock select LSB CLKIN_SEL1 Input clock select MSB I2C_ADDR Selection control for i2c address ClockBuilder Pro will allow a user to select similar functions to choose a single GPI input Fo...

Page 11: ... driver outx_cmos_str Sets the output impedance of the CMOS driver Table 5 2 OUTx_Mode vs Output Formats OUTx_MODE Driver Mode 0 off 1 CMOS on positive output only 2 CMOS on negative output only 3 dual CMOS outputs The recommended termination for each output format is shown in figures below Si5357 Reference Manual Output Clock Terminations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100...

Page 12: ... Zo 50Ω Zo 50Ω Rs Rs Zo Rdrv Set output driver to 25Ω mode Figure 5 2 LVCMOS Termination Option 2 Si5357 Reference Manual Output Clock Terminations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 12 Rev 0 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 12 ...

Page 13: ...he calculations below P PFD LF Mn Md R R R R R R VDD_XTAL VDDA VDDOA VDDOB VDDOC VDDOD VDDOE XA CLKIN_1 XB CLKIN_2 nCLKIN_2 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 N0b N0a N1b N1a O0b O0a O1b O1a O2b O2a O3b O3a O4b O4a Figure 6 1 Top Level Block Diagram Si5357 Reference Manual Programming the Volatile Memory Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales sk...

Page 14: ... are available in the custom part that you choose to re program PllRefFreq is given by the InFreq active clock input frequency and P as PllRefFreq InFreq P Table 6 1 Constraints for PLL Reference Frequency and VCO Frequency Field Name Value Description pllMinRefFreq 10 MHz The minimum reference frequency the PLL can tolerate pllMaxRefFreq 50 MHz The maximum reference frequency the PLL can tolerate...

Page 15: ...hsdivi 2 Now form MC2 groups of M 2 output frequencies Find the LCM of each group and find an integer I that can such that a vcoFreq I LCM can meet the constraint for vcoFreq in Table 6 1 Constraints for PLL Reference Frequency and VCO Frequency on page 14 b List the L groups that provide a legal vcoFreq i e a vcoFreq that satisfies the condition in step a c Choose the vcoFreq that has most number...

Page 16: ...able 6 4 Loop BW Options PLL_MODE Loop Bandwidth kHz PLL Ref Freq Min MHz PLL Ref Freq Max MHz 0 ILLEGAL IF PLL MODE IS ENABLED 1 350 10 15 2 250 10 15 3 175 10 15 4 500 15 30 5 350 15 30 6 250 15 30 7 175 15 30 8 500 30 50 9 350 30 50 10 250 30 50 11 175 30 50 This algorithm will result in a final solution for a VCO frequency vcoFreq that can then be used to calculate the O divider N divider and ...

Page 17: ...ther If some outputs have tight jitter requirements while others are relatively loose rearrange the clock outputs so that the critical outputs are the least susceptible to crosstalk These guidelines typically only need to be followed by those applications that wish to achieve the highest possible levels of jitter performance Because CMOS outputs have large pk pk swings and do not present a balance...

Page 18: ...e settings of all dividers that will result in the frequency plan When a valid divider solution space cannot be determined that frequency plan is not realizable in the Si5357 Table 6 6 Rxy to Register Field Mapping Divider Value Register Field Description R0_1 OUT0_1_DIV Driver divider ratio 0 disabled 1 63 divide value R2_3 OUT2_3_DIV Driver divider ratio 0 disabled 1 63 divide value R4_5 OUT4_5_...

Page 19: ... low z 1 high z OUTx _cmos_inv Sets the polarity of the two outputs 0 clk_p 1 clk_m OUTx _cmos_slew Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest OUTx _cmos_str CMOS output impedance control 0 50 Ω 1 25 Ω Table 6 8 Driver Mode Options drvxy_MODE Driver Mode 0 off 1 CMOS on positive output only 2 CMOS on negative output only Si5357 Reference Manual Programming th...

Page 20: ... A to bank B Spread spectrum enable fields IDxA_SS_ENA and IDxB_SS_ENA are the only exception and may be enabled disabled while bank is selected 0 bank A 1 bank B In a factory programmed part a pin the FS pin can be used for the same purpose as the control registers Once a control bit is set the backup divider values control the output frequency and that is described the equations below O Divider ...

Page 21: ..._den idxy 128 2 idxy_ss_step_num time frequency F0 Fmax F0 1 ssc 200 Fmin F0 1 ssc 200 Fmod one modulation cycle Fmod one modulation cycle F0 frequency time Fmin F0 1 ssc 100 Figure 6 2 Illustration Center and Down Spread SSC Clocks as Frequency vs Time Plots The table below shows the register fields and terms idxy_ss_step_num and idxy_ss_step_res idxy_ss_step_num is the number of frequency steps ...

Page 22: ...enable SSC idxy_ss_ena needs to be set and the right mode selected in idxy_ss_mode The number of output clocks in each frequency step idxy_ss_clk_num needs to be set to 1 and idxy_ss_step_den is the same as idxy_den and idxy_ss_step_intg is always zero The following flow needs to be followed to program the registers into Si5357 1 Write 0x01h to register 0x06h and put the Si5357 into the READY stat...

Page 23: ...O regulator ii The only filtering needed on each supply node is a 1 μF and a 0 1 μF placed as close as possible to that node iii The Si5357 EVBs have a much larger capacitance on the regulator end mainly to compensate for the regulator loop so that there is no oscillatory behavior from the regulators regardless of the voltage supply value set for that regulator The regulator supply design on the E...

Page 24: ...e Si5357 is actively locked to an input and is providing outputs Some register fields can be programed in either READY or ACTIVE mode READY ACTIVE whereas others can only be programmed in READY mode READY Device mode provides input on which mode applies to a register field a user intends to modify Table 8 1 Si5357 Register Map Register field name Address Base Bit length R W RW Description Device m...

Page 25: ... project file DESIGN_ID1 18 0 8 R DESIGN_ID2 19 0 8 R DESIGN_ID3 1A 0 8 R DESIGN_ID4 1B 0 8 R DESIGN_ID5 1C 0 8 R I2C_ADDR 21 0 7 R I2C mode device address Reset value is 110_0000 binary I2C_SCL_PUP_ENA 23 0 1 RW Enable 50 kohm pullup resistor on SCL pad READY ACTIVE I2C_SDA_PUP_ENA 23 1 1 RW Enable 50 kohm pullup resistor on SDA pad READY ACTIVE OMUX0_1_SEL0 25 0 2 RW Selects output mux clock for...

Page 26: ... before prescaler 1 PLL reference clock after prescaler 2 Clock from input buffer CLKIN_2 READY ACTIVE OMUX6_7_SEL1 28 4 3 RW Selects output mux clock for output clocks OUT6 OUT7 0 HSDIV0 1 HSDIV1 2 HSDIV2 3 HSDIV3 4 HSDIV4 5 ID0 6 ID1 7 Clock from OMUX4_5_SEL0 Note that the OMUX4_5_SEL1 value is forced to 7 whenever the PLL is disabled READY ACTIVE OMUX8_9_SEL0 29 0 2 RW Selects output mux clock ...

Page 27: ...plete configurations controlled by this bit Reconfiguration should be done on the unselected bank If ID0_CFG 0 running based off bank A then bank B may be freely reconfigured and once ready all changes will be applied to the ID once ID0_CFG 1 thus changing the ID from bank A to bank B Spread spec trum enable fields ID0A_SS_ENA and ID0B_SS_ENA are the only exception and may be enabled disabled whil...

Page 28: ...ze ID0A_SS_STEP_RES 40 0 15 RW Numerator of spread step size error term ID0B_INTG 42 0 15 RW The terms of an a b c desired di vider setting must be processsed into ID0B_INTG ID0B_RES and ID0B_DEN register terms intg floor a c b 128 c 512 READY if divider is cur rently driving the out put else READY ACTIVE ID0B_RES 44 0 15 RW res mod b 128 c ID0B_DEN 46 0 15 RW den c ID0B_SS_ENA 48 0 1 RW Spread sp...

Page 29: ...term ID1B_INTG 5A 0 15 RW The terms of an a b c desired di vider setting must be processsed into ID1A_INTG ID1A_RES and ID1A_DEN register terms intg floor a c b 128 c 512 READY if divider is cur rently driving the out put else READY ACTIVE ID1B_RES 5C 0 15 RW res mod b 128 c ID1B_DEN 5E 0 15 RW den c ID1B_SS_ENA 60 0 1 RW Spread spectrum enable This is the on ly bank configuration field which may ...

Page 30: ...zed from NVM READY PLL_MODE BE 2 4 RW Sets PLL BW See table 5 READY XOSC_CINT_ENA BF 7 1 RW Enabled integrated capacitance on XA and XB READY XOSC_CTRIM_XA C0 0 6 RW Load capacitance trim on XA READY XOSC_CTRIM_XB C1 0 6 RW Load capacitance trim on XB READY OUT0_1_MODE 7A 0 4 RW Software interpreted driver configura tion See table 3 READY OUT0_1_DIV 7B 0 6 RW Driver divider ratio 0 disabled 1 63 d...

Page 31: ...f the two outputs 0 no inversion 1 OUT5 inverted READY OUT4_5_CMOS_SLEW 8D 0 2 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 Slower 11 slowest READY OUT4_5_CMOS_STR 8D 2 1 RW CMOS output impedance control 0 50 Ohm 1 25 Ohm READY OUT6_7_MODE 98 0 4 RW Software interpreted driver configura tion See table 3 READY OUT6_7_DIV 99 0 6 RW Driver divider ratio 0 disabled 1 63 divide va...

Page 32: ...igh z READY OUT10_11_CMOS_INV AF 4 1 RW Sets the polarity of the two outputs 0 no inversion 1 OUT11 inverted READY OUT10_11_CMOS_SLEW B0 0 1 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 Slower 11 slowest READY OUT10_11_CMOS_STR B0 2 1 RW CMOS output impedance control 0 50 Ohm 1 25 Ohm READY OUT4_5_OE B6 3 1 RW output enable control for OUT4 OUT5 READY ACTIVE OUT6_7_OE B6 6 1 ...

Page 33: ...source 0 Disa bled 1 XOSC 2 CLKIN_2 3 Disabled READY Si5357 Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 33 Rev 0 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 33 ...

Page 34: ...RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal injury death physical or environmental damage Skyworks customers using or selling Skyworks products for use in such applications do so at the...

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