SH69P55A/K55A
27
T2
Internal clock
FF9E
FFFF
FF9C
FF9D
00
FF9C
FF9D
FF9F
FF9E
Up-counter
T2GO
Timer2 INT
Trigger Start (DEC = 0)
Count start
Count start
T2
Internal clock
F062
M - 1
F060
F061
00
F061
F062
FFFF
F060
Up-counter
T2GO
Timer2 INT
Trigger Start and Stop (DEC = 1)
Count start
Count start
F060
M
Count relooad
(4) Pulse Width Measurement Mode
In this mode, Timer2 is performed using a special function under the timer mode in which counting is started on an valid edge
of pulse that is input to the T2 pin. It is possible to measure the width of the pulse by reading the up-counter values. The
rising or falling edge of the T2 pin input is selected by the Timer2 pre-scaler register ($15) T2E (bit3). But the clock source of
the up-counter is the system internal clock selected by the Timer2 pre-scaler register ($15) T2SC (bit2-0). When the Timer2
control register ($27) T2GO (bit3) is set to 1, the contents of the up-counter is reset to “0000H”, automatically. Then a rising
(falling) edge signal on the T2 input pin triggers the up-counter to start counting. At the next falling (rising) edge, the counter
value is loaded to the Timer2 load register ($384 - $387), individually. Simultaneously, the Timer2 interrupt is generated if the
Interrupt enable register ($00) IET2 (bit1) is set to 1.
When the Timer2 control register ($27) DEC (bit2) is cleared to 0, the Timer2 is in the one-edge capture mode. If the rising
edge is selected as the counter-triggering signal, at the next falling edge, the Timer2 interrupt request is generated. At the
same time, the contents of the up-counter must be loaded to the Timer2 load register ($384 - $387) at first, then will be
cleared again and the counter is halted. When the next rising edge applies to the T2 input pin, the up-counter starts counting
for another measurement cycle.
When the Timer2 control register ($27) DEC (bit2) is set to 1, the Timer2 is in the double-edge capture mode. If the rising
edge is selected as the counter-triggering signal, at the next falling edge, the Timer2 interrupt request is generated. At the
same time, the contents of the up-counter must be loaded to the Timer2 load register ($384 - $387) at first, then the counter
continues counting. When the next rising edge applies to the T2 input pin, the Timer2 interrupt request is also generated. At
this time, the contents of the up-counter must be loaded to the Timer2 load register ($384 - $387) again, then the counter is
cleared and can be continued to start counting following measurement cycles.
In this mode, writing the Timer2 load register ($384 - $387) at any time cannot affect the up-counter operating anymore.
In this mode, the T2 pin input signal must follow certain constraints as in the external trigger timer mode. So, the limitation is
applied for the external clock period time (T
E
) described as follows:
T
E
(period time)
≥
1 * t
Timer clock
+ 2 *
∆
T;
∆
T = 20ns
T
E
(period time)
≥
(M * t
OSC
) + 2 *
∆
T
