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Sino Wealth SH69K55A, Manual

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Sino Wealth SH69K55A Manual Download Page 21

                                       

SH69P55A/K55A

 

 

21  

„

 

Port Interrupt 

The PORTB and PORTC are used as port interrupt sources. Since PORTB and PORTC are bit programmable I/Os, only 
when the PORTB and PORTC are selected as normal I/O input, the voltage transition from V

DD

 to GND applying to the digital 

input port can generate a port interrupt. When they are selected as analog input (such as ADC input), Port interrupt request 
cannot be generated. 
The interrupt control flags are mapped on $388 - $38A of the system register. They can be accessed by the read/write 
operation. Those flags are clear to ‘0’ at the initialization by the chip reset.   
Port interrupts can be used to wake up the CPU from the HALT or the STOP mode. 

System Register $388, $38A:

 Port Interrupt Enable Flags Register 

Address 

Bit 3 

Bit 2 

Bit 1 Bit 

0 

R/W

Remarks 

$388 

PBIEN.3 

PBIEN.2 

PBIEN.1

PBIEN.0

R/W

PORTB interrupt enable flags register 

$38A 

PCIEN.3 

PCIEN.2 

PCIEN.1

PCIEN.0

R/W

PORTC interrupt enable flags register 

PB/CIEN.n, (n = 0, 1, 2, 3) 
0: Disable port interrupt. (Power on initial) 
1: Enable port interrupt. 

System Register $389, $38B

: Port Interrupt Request Flags Register 

Address 

Bit 3 

Bit 2 

Bit 1 Bit 

0 

R/W

Remarks 

$389  PBIF.3 PBIF.2 PBIF.1 PBIF.0 

R/W

PORTB interrupt request flags register 

$38B 

PCIF.3 

PCIF.2 

PCIF.1 

PCIF.0 

R/W

PORTC interrupt request flags register 

PB/CIF.n, (n = 0, 1, 2, 3) 
0: Port interrupt is not presented. (Power on initial) 
1: Port interrupt is presented. 
Only writing these bits to “0” is available. 

Following is the port interrupt function block-diagram for reference. 

IRQEX

Interrupt CPU

IEEX

external interrupt

request generator

PC.3 - 0

Request Flag

(PCIF.3 - 0)

PCCR.3 - 0

Falling Edge

 Detector

PBIEN.3 - 0

PB.3 - 0

Request Flag

(PBIF.3 - 0)

PBCR.3 - 0

Falling Edge

 Detector

PCIEN.3 - 0

 

Port Interrupt Programming Notes: 

„

 Any one of PORTB & PORTC input pin transitions from V

DD

 to GND would set PBIF.x or PCIF.x to “1”, in spite of level of 

the other pin of PORTB and PORTC. 

„

 If PBIEN.x (or PCIEN.x) = 1and IEEX = 1, the x of PORTB (or PORTC) input pin transitions from V

DD

 to GND would 

generate an interrupt request (PBIF.x = 1 or PCIF.x = 1) and interrupt the CPU, in spite of level of the other pin of PORTB 
(or PORTC).   

Summary of Contents for SH69K55A

Page 1: ... Interrupt Oscillator Code Option Crystal Oscillator 32 768kHz 400kHz 8MHz Ceramic Resonator 400kHz 8MHz External RC Oscillator 400kHz 8MHz Internal RC Oscillator 4MHz 5 One Built in PLL Oscillator 1 2 4 8MHz Instruction Cycle Time 4 fOSC 10 Channels 10 Bit Resolution Analog Digital Converter ADC 2 Channel Tone Generators Built in Automatic Key Scanner Zero Cross Detect Function for AC Power Line ...

Page 2: ...2 PORTE 3 COM5 LED_C5 SEG20 PORTE 2 COM6 LED_C6 SEG19 PORTE 1 COM7 SEG18 PORTE 0 COM8 SEG17 PORTH 3 SEG16 PORTH 2 SEG15 PORTH 1 SEG14 PORTH 0 SEG13 PORTI 3 SEG12 PORTI 2 SEG11 PORTI 1 SEG10 44 43 42 41 40 39 38 37 34 35 36 PORTK 1 PORTK 0 PORTF 2 SEG7 LED_S7 PORTA 1 SEG2 LED_S2 KEY_I2 RESET PORTC 3 PORTD 0 COM4 LED_C4 KEY_04 PORTD 1 COM3 LED_C3 KEY_03 PORTD 2 COM2 LED_C2 KEY_02 PORTD 3 COM1 LED_C1...

Page 3: ...E 0 COM8 SEG17 PORTB 1 AN1 PORTB 2 AN2 PORTB 3 AN3 PORTG 0 PWM PORTG 1 TONE AN9 PORTG 2 VREF T0 PORTB 0 AN0 PORTC 0 PLL_C OSCO PORTC 1 OSCI PORTC 2 PORTG 3 T2 AN8 RESET PORTC 3 PORTA 0 SEG1 LED_S1 KEY_I1 PORTA 1 SEG2 LED_S2 KEY_I2 SH69P55A 69K55A 28Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PORTA 3 SEG4 LED_S4 PORTI 0 SEG9 PORTB 2 AN2 PORTB 1 AN1 PORTB 0 AN0 POR...

Page 4: ... 376 X 4 Bits Data Memory 10ch X 10bits ADC 1 X 8 2 Bits PWM Power Circuit PORTB 3 0 AN3 AN0 PORTF 3 0 SEG8 SEG5 LED_S8 LED_S5 KEY_I5 PORTE 3 0 COM5 COM8 LED_C5 LED_C6 SEG20 SEG17 PORTA 3 0 SEG4 SEG1 LED_S4 LED_S1 KEY_I4 KEY_I1 PORTH 4 bit PORTC 3 PORTH 3 0 SEG16 SEG13 Tone generator 1 PORTC 2 0 Tone generator 2 PORTG 3 0 T2 T0 VREF TONE PWM AN8 AN9 PORTG 4 bit PORTI 3 0 SEG12 SEG9 PORTI 4 bit POR...

Page 5: ... Interrupt Active falling edge by system register setup Bit programmable I O open drain 12 14 13 9 14 35 36 43 GND P Ground pin 13 15 14 15 16 VDD P Power supply pin 17 14 19 16 18 15 20 17 PORTA 3 0 SEG4 SEG1 LED_S4 LED_S1 KEY_I4 KEY_I1 I O O O I Bit programmable I O SEG4 SEG1 signal output for LCD display SEG4 SEG1 signal output for LED display Input for automatic key scan 18 19 21 PORTF 0 SEG5 ...

Page 6: ...edge by system register setup ADC input channel 2 0 41 1 4 47 PORTB 3 AN3 I O I I Bit programmable I O Vector Interrupt Active falling edge by system register setup ADC input channel 3 42 2 5 48 PORTG 0 PWM I O O Bit programmable I O PWM output 43 3 6 49 PORTG 1 TONE AN9 I O O I Bit programmable I O TONE Generator output ADC input channel 9 Which I Input O Output P Power Z High impedance OTP Progr...

Page 7: ...nstant RTNW instructions The TBR and AC are placed by an offset address in program ROM TJMP instruction branch into address PC11 PC8 X 28 TBR AC The address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bit0 into AC 1 5 Data Pointer The Data Pointer can indirectly address data memory Pointer address is located in register DPH 3 bits DPM 3 ...

Page 8: ...a pointer for INX low nibble register 11 DPM 2 DPM 1 DPM 0 R W Data pointer for INX middle nibble register 12 DPH 2 DPH 1 DPH 0 R W Data pointer for INX high nibble register 13 VREF ACR2 ACR1 ACR0 R W Bit2 0 A D port configuration control register Bit3 Select Internal External reference voltage register 14 ADCON CH2 CH1 CH0 R W Bit2 0 ADC channel control register Bit3 ADC module operate control re...

Page 9: ...R Bit3 0 the result of key scan on KEY_I5 1 register 2E RLCD PS2 PS1 PS0 R W Bit2 0 Configuration the segment register Bit3 LCD bias resistor set register 2F GO DONE TADC1 TADC0 R W Bit2 1 A D Conversion Time control register Bit3 ADC startup status flag register 380 RDT 3 RDT 2 RDT 1 RDT 0 R W ROM Data table address data register 381 RDT 7 RDT 6 RDT 5 RDT 4 R W ROM Data table address data registe...

Page 10: ...CR 3 PPICR 2 PPICR 1 PPICR 0 R W PORTI pull high control register 3A1 PPJCR 3 PPJCR 2 PPJCR 1 PPJCR 0 R W PORTJ pull high control register 3A2 PPKCR 1 PPKCR 0 R W PORTK pull high control register 3A3 TG1 3 TG1 2 TG1 1 TG1 0 R W Tone generator 1 low nibble register 3A4 TG1 7 TG1 6 TG1 5 TG1 4 R W Tone generator 1 middle nibble register 3A5 TG1 11 TG1 10 TG1 9 TG1 8 R W Tone generator 1 high nibble ...

Page 11: ...MER2 interrupt service routine 004 JMP Jump to External interrupts service routine JMP instruction can be replaced by any instruction 3 2 Bank Switch Mapping Program Counter PC11 PC0 can only address 4K ROM Space The bank switch technique is used to extend the CPU address space The lower 2K of the CPU address space maps to the lower 2K of ROM space BANK0 The upper 2K of the CPU address space maps ...

Page 12: ...2 PE 1 PE 0 0000 0000 0D PF 3 PF 2 PF 1 PF 0 0000 0000 0E TBR 3 TBR 2 TBR 1 TBR 0 xxxx uuuu 0F INX 3 INX 2 INX 1 INX 0 xxxx uuuu 10 DPL 3 DPL 2 DPL 1 DPL 0 xxxx uuuu 11 DPM 2 DPM 1 DPM 0 xxx uuu 12 DPH 2 DPH 1 DPH 0 xxx uuu 13 VREF ACR2 ACR1 ACR0 0000 uuuu 14 ADCON CH2 CH1 CH0 0000 0uuu 15 T2E T2SC 2 T2SC 1 T2SC 0 0000 uuuu 16 FS1 FS0 OXS OXON 0000 uuuu 17 LVR 0 18 PACR 3 PACR 2 PACR 1 PACR 0 0000...

Page 13: ...xxx uuuu 383 RDT 15 RDT 14 RDT 13 RDT 12 xxxx uuuu 384 T2D 3 T2D 2 T2D 1 T2D 0 xxxx xxxx 385 T2D 7 T2D 6 T2D 5 T2D 4 xxxx xxxx 386 T2D 11 T2D 10 T2D 9 T2D 8 xxxx xxxx 387 T2D 15 T2D 14 T2D 13 T2D 12 xxxx xxxx 388 PBIEN 3 PBIEN 2 PBIEN 1 PBIEN 0 0000 0000 389 PBIF 3 PBIF 2 PBIF 1 PBIF 0 0000 0000 38A PCIEN 3 PCIEN 2 PCIEN 1 PCIEN 0 0000 0000 38B PCIF 3 PCIF 2 PCIF 1 PCIF 0 0000 0000 38C KEYIE ADIE ...

Page 14: ...uu 3A4 TG1 7 TG1 6 TG1 5 TG1 4 xxxx uuuu 3A5 TG1 11 TG1 10 TG1 9 TG1 8 xxxx uuuu 3A6 TG2 3 TG2 2 TG2 1 TG2 0 xxxx uuuu 3A7 TG2 7 TG2 6 TG2 5 TG2 4 xxxx uuuu 3A8 TG2 11 TG2 10 TG2 9 TG2 8 xxxx uuuu 3A9 TV1 3 TV1 2 TV1 1 TV1 0 xxxx uuuu 3AA TG1EN TV1 6 TV1 5 TV1 4 xxxx uuuu 3AB TV2 3 TV2 2 TV2 1 TV2 0 xxxx uuuu 3AC TG2EN TV2 6 TV2 5 TV2 4 xxxx uuuu 3AD A1 A0 xx uu 3AE A5 A4 A3 A2 xxxx uuuu 3AF A9 A8...

Page 15: ... Oscillator 32 768kHz or 400kHz 8MHz OSCI OSCO C1 C2 Crystal PLL_C 2 Ceramic Resonator 400kHz 8MHz OSCI OSCO C1 C2 Ceramic PLL_C 3 RC Oscillator 400kHz 8MHz OSCI ROSC VDD OSCO PLL_C External RC 4 RC Oscillator 4MHz OSCI OSCO PLL_C Internal RC 5 PLL Oscillator 1 2 4 8MHz OSCI OSCO C1 C2 32 768 kHz PLL_C C3 2200p RPLL 100K Note If the external RC oscillator is selected OSCO pin is used as the I O po...

Page 16: ... R W Clock source is selected as PLL 0 0 1 1 R W PLL provides 8 126MHz clock signal for clock source LVR voltage range must be selected as 4V in the code option 0 1 1 1 R W PLL provides 4 063MHz clock signal for clock source 1 0 1 1 R W PLL provides 2 031MHz clock signal for clock source 1 1 1 1 R W PLL provides 1 016MHz clock signal for clock source Note 1 Usage of PLL First configure the FS1 and...

Page 17: ...HC 49U S 4 000MHz Vectron International 4MHz 8 15pF 8 15pF 49S 4 000M F16E Shenzhen DGJB Electronic Co Ltd HC 49U S 8 000MHz Vectron International 8MHz 8 15pF 8 15pF 49S 8 000M F16E Shenzhen DGJB Electronic Co Ltd Notes 1 Capacitor values are used for design guidance only 2 These capacitors were tested with the crystals listed above for basic start up and operation They are not optimized 3 Be care...

Page 18: ... R W PORTC data register 0B PD 3 PD 2 PD 1 PD 0 R W PORTD data register 0C PE 3 PE 2 PE 1 PE 0 R W PORTE data register 0D PF 3 PF 2 PF 1 PF 0 R W PORTF data register 38E PG 3 PG 2 PG 1 PG 0 R W PORTG data register 38F PH 3 PH 2 PH 1 PH 0 R W PORTH data register 390 PI 3 PI 2 PI 1 PI 0 R W PORTI data register 391 PJ 3 PJ 2 PJ 1 PJ 0 R W PORTJ data register 392 PK 1 PK 0 R W PORTK data register Syst...

Page 19: ... PPFCR 0 R W PORTF pull high control register 39E PPGCR 3 PPGCR 2 PPGCR 1 PPGCR 0 R W PORTG pull high control register 39F PPHCR 3 PPHCR 2 PPHCR 1 PPHCR 0 R W PORTH pull high control register 3A0 PPICR 3 PPICR 2 PPICR 1 PPICR 0 R W PORTI pull high control register 3A1 PPJCR 3 PPJCR 2 PPJCR 1 PPJCR 0 R W PORTJ pull high control register 3A2 PPKCR 1 PPKCR 0 R W PORTK pull high control register PA B ...

Page 20: ... be output 0 Port Control Register PCR 394 xx11B 395 396 1111B 397 0011B and Port Data Register PDR 38F xx00B and 390 391 0000B 392 0000B In 28pin package PORTD PORTF PORTH PORTI 3 2 and PORTK must be selected to be output 0 Port Control Register PCR 1B 1D 394 1111B 395 11xxB 397 0011B and Port Data Register PDR 0B 0D 38F 0000B 390 00xxB 392 0000B In SH69P55A 69K55A each output port contains a lat...

Page 21: ... 2 3 0 Disable port interrupt Power on initial 1 Enable port interrupt System Register 389 38B Port Interrupt Request Flags Register Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 389 PBIF 3 PBIF 2 PBIF 1 PBIF 0 R W PORTB interrupt request flags register 38B PCIF 3 PCIF 2 PCIF 1 PCIF 0 R W PORTC interrupt request flags register PB CIF n n 0 1 2 3 0 Port interrupt is not presented Power on initial 1 P...

Page 22: ...overflow from FF to 00 Timer Load Register Since the register H controls the physical READ and WRITE operations Please follow these steps Write Operation Low nibble first High nibble to update the counter Read Operation High Nibble first Low nibble followed Load Reg H 8 bit timer counter Load Reg L Latch Reg L 7 2 Timer0 and Timer1 Mode Register The Timer can be programmed in several different pre...

Page 23: ...ilable when the oscillator type is selected as 32 768kHz Otherwise the T1S register must be cleared to 0 7 3 External Clock Event T0 as Timer0 Source When external clock event T0 input as Timer0 source it is synchronized with the CPU system clock The external source must follow certain constraints The system clock samples it in instruction frame cycle Therefore it is necessary to be high at least ...

Page 24: ...tten or the counter counts overflow from FFFF to 0000 Timer Load Register Since the register H controls the physical READ and WRITE operations Please follow these steps Write Operation Low nibble first High nibble to update the counter Read Operation High nibble first Low nibble followed Load Reg H 16 bit timer counter Load Reg L Latch Reg L Latch Reg H 7 6 Timer2 Control Register The Timer2 can b...

Page 25: ...transition T2 input 1 X X X R W Increment on low to high transition T2 input 2 External Event Counter Mode In this mode Timer2 is performed using the external clock via T2 pin shared with PORTG3 Either the rising or falling edge can be selected with the external trigger controlled by the Timer2 pre scaler register 15 T2E bit3 The contents of the Timer2 load register 384 387 are loaded into the up ...

Page 26: ...e the highest nibble 387 is written The T2 pin input signal must follow certain constraints The system clock samples it in instruction frame cycle Therefore it is necessary to be high at least 1 2 tTimer clock and low at least 1 2 tTimer clock In this mode the Timer clock is selected by the Timer2 pre scaler register So the limitation is applied to the external clock period time TE described as fo...

Page 27: ... to 0 the Timer2 is in the one edge capture mode If the rising edge is selected as the counter triggering signal at the next falling edge the Timer2 interrupt request is generated At the same time the contents of the up counter must be loaded to the Timer2 load register 384 387 at first then will be cleared again and the counter is halted When the next rising edge applies to the T2 input pin the u...

Page 28: ...is in the double edge capture operation The limitation is applied for the T2 input signal high or low level period described as follows TE high or low level period time 14 tSystem clock TE high or low level period time 14 4 tOSC T2 Internal clock 0002 0000 0001 N M 0002 N 1 0000 Up counter T2GO Timer2 INT One edge capture DEC 0 Count start Count start 0000 M T2 counter reg XXXX 0001 N Capture Capt...

Page 29: ... and segment output low Before use the LCD driver LEDEN bit3 in 2B must be cleared LCD Control Register 29 Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 29 LCDON DUTY2 DUTY1 DUTY0 R W Bit2 0 Set duty and com register Bit3 LCD display on control register 0 X X X R W LCD OFF 1 X X X R W LCD ON X 0 X X R W PORTD and PORTE as I O ports X 1 0 0 R W Set 1 4 duty PORTD3 0 as COM1 4 PORTE as I O ports X 1 0...

Page 30: ...y will change in proportion to the variation of OSC frequency in spite of OSC type and the FOSC Code Option See Page 56 for detail COM FOSC Code Option LCD Frame Frequency Osc Range EXAMPLE 00 fosc 40 960 4M 8M fOSC 4M fLCD 97 5Hz 01 fosc 20 480 2M 4M fOSC 2M fLCD 97 5Hz 10 fosc 10 240 1M 2M fOSC 1M fLCD 97 5Hz 11 fosc 5 120 400k 1M fOSC 500k fLCD 97 5Hz 4 xx fosc 320 32 768k fOSC 32 768k fLCD 102...

Page 31: ... shared as the SEG20 17 for LCD display SEGs and COMs shall be configured correctly before the LCD is turned on Configuration of LCD RAM Area LCD 1 4 duty 1 3 bias COM uses COM1 4 SEG uses SEG1 20 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address COM4 COM3 COM2 COM1 Address COM4 COM3 COM2 COM1 300 SEG1 SEG1 SEG1 SEG1 30A SEG11 SEG11 SEG11 SEG11 301 SEG2 SEG2 SEG2 SEG2 30B SEG12 SEG12 SEG12 SEG12 302...

Page 32: ...7 330 SEG17 SEG17 311 SEG18 SEG18 SEG18 SEG18 331 SEG18 SEG18 Configuration of LCD RAM Area LCD 1 8 duty 1 4 bias COM uses COM1 8 SEG uses SEG1 16 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address COM4 COM3 COM2 COM1 Address COM8 COM7 COM6 COM5 300 SEG1 SEG1 SEG1 SEG1 320 SEG1 SEG1 SEG1 SEG1 301 SEG2 SEG2 SEG2 SEG2 321 SEG2 SEG2 SEG2 SEG2 302 SEG3 SEG3 SEG3 SEG3 322 SEG3 SEG3 SEG3 SEG3 303 SEG4 SEG4...

Page 33: ...it 2 Bit 1 Bit 0 R W Remarks 2E RLCD R W Bit3 Set LCD bias resistor register 0 X X X R W R1 R2 R3 90k 1 X X X R W R1 R2 R3 10k X X X X R W R1 R2 R3 3k if KEYEN 1 When a large LCD panel is used user can set the value of 2E to increase the bias current for better LCD performance But it will cost more power when the smaller divider resistances are used When the CPU is in STOP mode the COM1 8 and SEG1...

Page 34: ...SH69P55A K55A 34 LCD Waveform 1 4 duty 1 3 bias LCD Waveform SEG V1 COM4 COM3 COM2 COM1 V2 V3 V1 V2 V3 V1 V2 V3 V1 V2 V3 V1 GND V2 V3 GND GND GND GND ...

Page 35: ...SH69P55A K55A 35 1 6 duty 1 3 bias LCD Waveform SEG V1 COM4 COM3 COM2 COM1 V2 V3 V1 V2 V3 V1 V2 V3 V1 V2 V3 V1 GND V2 V3 GND GND GND GND ...

Page 36: ...SH69P55A K55A 36 1 8 duty 1 4 bias LCD Waveform V1 V2 V3 GND V1 V2 V3 GND V1 V2 V3 GND VDD V1 V2 V3 GND SEG COM3 COM2 COM1 VDD VDD VDD ...

Page 37: ... R W Bit1 0 Set duty register Bit2 Turn on LED driver register Bit3 Enable LED driver register 0 X X X R W LCD enable 1 X X X R W LED enable 1 0 X X R W LED driver off 1 1 X X R W LED driver on 1 X 0 0 R W PORTD and PORTE are normal I O port 1 X 0 1 R W 1 4 duty PORTD3 0 is shared as COM1 4 for LED display and PORTE3 2 is normal I O port 1 X 1 0 R W 1 5 duty PORTD3 0 and PORTE3 is shared as COM1 5...

Page 38: ...SEG3 303 SEG4 SEG4 SEG4 SEG4 323 SEG4 304 SEG5 SEG5 SEG5 SEG5 324 SEG5 305 SEG6 SEG6 SEG6 SEG6 325 SEG6 306 SEG7 SEG7 SEG7 SEG7 326 SEG7 307 SEG8 SEG8 SEG8 SEG8 327 SEG8 Configuration of LCD RAM Area 1 6 duty COM1 6 SEG1 8 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address COM4 COM3 COM2 COM1 Address COM6 COM5 300 SEG1 SEG1 SEG1 SEG1 320 SEG1 SEG1 301 SEG2 SEG2 SEG2 SEG2 321 SEG2 SEG2 302 SEG3 SEG3 S...

Page 39: ...t duty period of one frame but it does not work during the last duty period of the next frame For instance in 1 4 duty mode the key scanner only works a duty period for every two frames and it does not work during the rest 9 duty periods of the two frames Once the end of the key scan reaches the key interrupt request flag would be set KEYIF whether a key is pressed or not In LCD mode the key inter...

Page 40: ...lear KEYNUM0 and KEYNUM1 flags at the beginning of the key scan process KEYEND flag would keep 1 during the whole key scan process and it would be cleared at the end of the scan process For instance in 1 4 duty mode KEYEND keeps 1 during the working duty period and keeps 0 during the rest 9 duty periods KEYNUM0 and KEYNUM1 would be cleared at the beginning of the working duty period and would be s...

Page 41: ...41 An Example of the program flow of customer applications Start Clear KEYIF KEYIF 1 KEYNUM0 1 KEYNUM1 1 Store KEYC and KEYL Other Routines Yes No Yes No Yes No Key pressed Single key pressed Identify the pressed key ...

Page 42: ... Bit 2 Bit 1 Bit 0 R W Remarks 3C2 ACR3 CH3 R W Bit2 ADC channel control register Bit3 A D port configuration control register 1 X R W Set analog channels X 1 R W ADC channels control register Systems Register Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 14 ADCON CH2 CH1 CH0 R W Bit2 0 ADC channel control register Bit3 ADC module operate control register 0 X X X R W Disable ADC module 1 X X X R W E...

Page 43: ...CH0 Remarks 0 0 0 0 ADC Channel AN0 0 0 0 1 ADC Channel AN1 0 0 1 0 ADC Channel AN2 0 0 1 1 ADC Channel AN3 0 1 0 0 ADC Channel AN4 0 1 0 1 ADC Channel AN5 0 1 1 0 ADC Channel AN6 0 1 1 1 ADC Channel AN7 1 x x 0 ADC Channel AN8 1 x x 1 ADC Channel AN9 ...

Page 44: ...PORTB 0 AN0 PORTB 1 AN1 PORTB 2 AN2 PORTB 3 AN3 PORTJ 0 AN4 PORTJ 1 AN5 PORTJ 2 AN6 PORTJ 3 AN7 0000 0001 0010 0011 0100 0101 0110 0111 CH3 CH0 VREFS PORTG 3 AN8 1xx0 PORTG 1 AN9 1xx1 A D Converter Block Diagram Notes Select A D Conversion Time make sure that A D Conversion Time 25µs When the A D conversion is complete an ADC interrupt occurs if the ADC interrupt is enabled The analog input channe...

Page 45: ...en the VREF pin and the GND pin to provide the current input into the SH69P55A 69K55A from the VREF pin figure 3 The method that shows in figure 4 also can set up the External reference voltage but the current consume of the hole system will increase obviously VDD 5 0V R1 R2 500Ω 10mA increases the dashed frames in all the figures are 0 1µF capacitances in order to reducing the disturbance in the ...

Page 46: ...ty cycle high active Default 1 X X X R W PWM output negative mode of duty cycle low active The PWM output pin is shared with PORTG 0 tOSC is the OSC clock If the PLL is enable tOSC is the PLL frequency otherwise tOSC is the OSC clock Systems Register 21 22 PWM Period Control Register PWMP Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 21 PP 3 PP 2 PP 1 PP 0 R W PWM period low nibble register 22 PP 7 ...

Page 47: ... tPWM 7FH X tPWM 80H X tPWM 80H X tPWM 80H X tPWM 01 02 03 7F 80 BF C0 01 02 03 7F 80 BF C0 01 02 03 7F 80 BF C0 01 02 03 7F 80 BF C0 01 02 03 7F 80 BF C0 Period Cycle0 C0H X tPWM Period Cycle1 C0H X tPWM Period Cycle2 C0H X tPWM Period Cycle3 C0H X tPWM Period Cycle0 C0H X tPWM 8 2 bit PWM Waveform Programming Notes 1 Select the PWM module system clock 2 Set the PWM period cycle by writing proper...

Page 48: ... output PWMS 0 PWM output duty cycle 7FH X tPWM PWM output PWMS 1 PWM output period cycle F0H X tPWM PP 7 PP 0 F0H PD 7 PD 0 7FH PDF 1 PDF 0 00H PWM Output Example PWM clock tPWM 01 02 03 04 05 06 07 08 09 0A 0B 0C0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C0D 01 02 03 04 05 06 07 08 Write PP 7 PP 0 0DH Write PD 7 PD 0 07H PWM output PWMS 0 Period cycle 0FH X tPWM Duty cycle 06H X tPWM Period cycl...

Page 49: ...Bit3 Low Voltage Reset flag register Read and Write 0 only 0 X X X R W No Low Voltage Reset 1 X X X R W Low Voltage Reset 14 ROM Data Table RDT System Register Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 380 RDT 3 RDT 2 RDT 1 RDT 0 R W ROM Data table address data register 381 RDT 7 RDT 6 RDT 5 RDT 4 R W ROM Data table address data register 382 RDT 11 RDT 10 RDT 9 RDT 8 R W ROM Data table address d...

Page 50: ...nable register 3AB TV2 3 TV2 2 TV2 1 TV2 0 R W Tone generator 2 volume low nibble register 3AC TG2EN TV2 6 TV2 5 TV2 4 R W Bit2 0 Tone generator 2 volume high nibble register Bit3 Tone generator 2 enable register The volume control register is 7 bit register used to control the output level of the tone generator TGxEN Tone generator x enabl 0 Tone generator x disable default 1 Tone generator x ena...

Page 51: ...358 E9A 1396 7 0 02 B3 246 94 2025 817 246 91 0 01 F6 1480 0 338 EAE 1479 3 0 05 C4 261 63 1911 889 261 64 0 01 G6 1568 0 319 EC1 1567 4 0 04 C4 277 18 1804 8F4 277 16 0 01 G6 1661 2 301 ED3 1661 1 0 01 D4 293 66 1703 959 293 60 0 02 A6 1760 0 284 EE4 1760 6 0 03 D4 311 13 1607 9B9 311 14 0 00 A6 1864 7 268 EF4 1865 7 0 05 E4 329 63 1517 A13 329 60 0 01 B6 1975 5 253 F03 1976 3 0 04 F4 349 23 1432...

Page 52: ...3 F2B 1173 7 0 08 D3 146 83 1703 959 146 80 0 02 D6 1244 5 201 F37 1243 8 0 06 D3 155 56 1607 9B9 155 57 0 00 E6 1318 5 190 F42 1315 8 0 21 E3 164 81 1517 A13 164 80 0 01 F6 1396 9 179 F4D 1396 7 0 02 F3 174 61 1432 A68 174 58 0 02 F6 1480 0 169 F57 1479 3 0 05 F3 185 00 1351 AB9 185 05 0 03 G6 1568 0 159 F61 1572 3 0 28 G3 196 00 1276 B04 195 92 0 04 G6 1661 2 150 F6A 1666 7 0 33 G3 207 65 1204 B...

Page 53: ... or writing the system register 1E the watchdog timer should re count before the overflow happens System Register 1E Watchdog Timer WDT Address Bit 3 Bit 2 Bit 1 Bit 0 R W Remarks 1E WDT WDT 2 WDT 1 WDT 0 R W R Bit2 0 Watch dog timer control register Bit3 Watchdog timer overflow flag register read only X 0 0 0 R W Watch dog timer out period 4096ms X 0 0 1 R W Watch dog timer out period 1024ms X 0 ...

Page 54: ...Interrupt Generated Interrupt Accepted Vector Generated Stacking Fetch Vector address Reset IE X Start at vector address Inst cycle 1 2 3 4 5 Interrupt Servicing Sequence Diagram Interrupt Nesting During the SH6610D CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting int...

Page 55: ...ster PB CIF n n 0 1 2 3 0 Port interrupt is not presented Default 1 Port interrupt is presented Only writing these bits to 0 is available Application Notes Any one of PORTB PORTC input pin transitions from VDD to GND would set PBIF x or PCIF x to 1 in spite of level of the other pin of PORTB and PORTC If PBIEN x or PCIEN x 1and IEEX 1 the x of PORTB or PORTC input pin transitions from VDD to GND w...

Page 56: ... PCCR 3 0 Falling Edge Detector PBIEN 3 0 PB 3 0 Request Flag PBIF 3 0 PBCR 3 0 Falling Edge Detector ADC Completion Detector ADC Request Flag ADIF ADC_ON KEY Scan Completion Detector KEY_Scan Request Flag KEYIF KEYEN PCIEN 3 0 ADIE KEYIE Port including other external sources Interrupt Function Block diagram ...

Page 57: ...l RC oscillator mode fOSC 4MHz the warm up counter prescaler divide ratio is 1 2 13 8192 2 In External RC oscillator mode fOSC 400kHz 8MHz the warm up counter prescaler divide ratio is 1 2 13 8192 3 In Crystal oscillator or Ceramic resonator mode the warm up counter prescaler divide ratio is 1 2 13 8192 4 In 32 768kHz mode the warm up counter prescaler divide ratio is 1 2 13 8192 B WDT Reset LVR R...

Page 58: ...stal Oscillator 400kHz 8MHz 100 32 768kHz Crystal Oscillator b Watch Dog Timer WDT 0 Enable WDT function default 1 Disable WDT function c Low Voltage Reset LVR 0 Disable LVR function default 1 Enable LVR function d LVR voltage Range LVR0 0 4V LVR voltage default 1 2 5V LVR voltage e Chip Pin Reset RST 0 Enable default 1 Disable Select RESET pin as PORTC3 f OSC Clock Range Select FOSC 1 0 00 4MHz O...

Page 59: ...xxx xxxx AC Mx AC EORM X B 00100 1bbb xxx xxxx AC Mx Mx AC OR X B 00101 0bbb xxx xxxx AC Mx AC ORM X B 00101 1bbb xxx xxxx AC Mx Mx AC AND X B 00110 0bbb xxx xxxx AC Mx AC ANDM X B 00110 1bbb xxx xxxx AC Mx Mx AC SHR 11110 0000 000 0000 0 AC 3 AC 0 CY AC shift right one bit CY 1 2 Immediate Type Mnemonic Instruction Code Function Flag Change ADI X I 01000 iiii xxx xxxx AC Mx I CY ADIM X I 01001 ii...

Page 60: ...10101 xxxx xxx xxxx PC X if AC 1 1 BA2 X 10110 xxxx xxx xxxx PC X if AC 2 1 BA3 X 10111 xxxx xxx xxxx PC X if AC 3 1 CALL X 11000 xxxx xxx xxxx ST CY PC 1 PC X Not include p RTNW H L 11010 000h hhh llll PC ST TBR hhhh AC Illl RTNI 11010 1000 000 0000 CY PC ST CY HALT 11011 0000 000 0000 STOP 11011 1000 000 0000 JMP X 1110p xxxx xxx xxxx PC X Include p TJMP 11110 1111 111 1111 PC PC11 PC8 TBR AC NO...

Page 61: ...very sensitive therefore four jumpers are needed VDD VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram For few OTP chip with more VDD pads the VDD pads should be connected together OTP Chip VPP VDD SCK SDA GND To Application Circuit Jumper Application PCB OTP Writer The recommended step is the followings 1 The jumper is Open to separate the...

Page 62: ...utput pins unloaded Execute NOP instruction WDT off ADC disable LVR off LCD off Key scan disable Operating Current IOP 12 20 µA fOSC 32 768kHz VDD 5 0V All output pins unloaded Execute NOP instruction WDT off ADC disable LVR off LCD off Key scan disable 1 8 mA fOSC 8MHz VDD 5 0V All output pins unloaded all input pins is not floating CPU stop HALT mode WDT off LVR off LCD off 1 3 mA fOSC 4MHz VDD ...

Page 63: ...idth tIPW tIW 2 ns RESET pulse width tRESET 10 µs Low active VDD 5 0V WDT Period tWDT 1 ms VDD 5 0V PLL Frequency Variation F F 0 6 Average frequency of continuous 256 clocks Frequency Stability RC F F 15 External ROSC Oscillator Include chip to chip variation VDD 5V TA 25 C Frequency Stability RC F F 5 Internal ROSC Oscillator fOSC 4MHz Include chip to chip variation VDD 5V TA 25 C A D Converter ...

Page 64: ...SH69P55A K55A 64 Timing Waveform a System Clock Timing Waveform T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 T4 fOSC System Clock tCY b T0 T2 Input Waveform tIW tIPW L tIPW H T0 T2 input signal ...

Page 65: ...Resistor vs Frequency VDD 5V 0 1 2 3 4 5 6 7 8 1 10 100 Typical RC Oscillator Resistance Rosc kΩ Frequency fosc MHz b External RC Oscillator Operation Voltage vs Frequency External RC Oscillator Operation Voltage vs Frequency Rosc 7 5kΩ 6 2 6 3 6 4 6 5 6 6 6 7 0 1 2 3 4 5 6 7 8 External RC Oscillator Operation Voltage VDD V Frequency fosc MHz ...

Page 66: ... AC Power line PORTG 0 is used as PWM output PORTB are used as ADC ports SH69P55A 69K55A VDD OSCI PORTC2 OSCO PORTC1 VDD 10uF 10k 8MHz C3 12p RESET C4 12p 0 1uF PORTC3 GND PORTA 0 PORTA 2 PORTA 1 PORTA 3 PORTF 0 PORTF 2 PORTF 1 PORTF 3 PORTD 0 PORTD 2 PORTD 1 PORTD 3 PORTE 3 PORTE 2 PORTG 1 PORTB PORTI0 AC power ADC input VDD R2 1k Q1 SPEAKER R3 1M Zero detect for AC power line PWM output R4 R5 R6...

Page 67: ...ect function for AC Power line PORTG 0 is used as PWM output PORTB are used as ADC ports VDD OSCI PORTC2 OSCO PORTC1 RESET PORTC3 GND SEG1 SEG3 SEG2 SEG4 SEG5 SEG7 SEG6 SEG8 COM1 COM3 COM2 COM4 PORTG 1 PORTB PORTK 0 PORTG 0 LCD R4 R5 R6 R7 R8 R9 R10 R11 R12 VDD 10uF 10k 8MHz C3 12p C4 12p 0 1uF AC power ADC input R3 1M Zero detect for AC power line PWM output VDD R2 1k Q1 SPEAKER 47k X 4 47k X 5 S...

Page 68: ...SH69P55A K55A 68 Ordering Information Part No Package SH69P55AF SH69K55AF 44 QFP SH69P55AM SH69K55AM 28 SOP SH69P55A SH69K55A 32 DIP ...

Page 69: ... 0 50Max A2 0 079 0 008 2 00 0 2 0 004 0 1 b 0 012 Typ 0 30 Typ c 0 006 0 002 0 15 0 05 D 0 394 0 004 10 00 0 10 E 0 394 0 004 10 00 0 10 e 0 031 Typ 0 80 Typ GD 0 488 NOM 12 40 NOM GE 0 488 NOM 12 40 NOM HD 0 519 0 008 13 20 0 20 HE 0 519 0 008 13 20 0 20 0 035 0 002 0 88 0 05 L 0 006 0 15 L1 0 063 Typ 1 60 Typ y 0 004 Max 0 10 Max θ 0 7 0 7 Notes 1 Dimensions D and E do not include resin fins 2 ...

Page 70: ...0 b 0 002 0 05 0 010 0 004 0 25 0 10 c 0 002 0 05 D 0 705 0 020 17 91 0 51 E 0 291 0 299 7 39 7 59 e 0 050 0 006 1 27 0 15 e1 0 376 NOM 9 40 NOM HE 0 394 0 417 10 01 10 60 L 0 036 0 008 0 91 0 20 LE 0 055 0 008 1 40 0 20 S 0 043 Max 1 09 Max y 0 004 Max 0 10 Max θ 0 10 0 10 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e1 is for P...

Page 71: ...18 0 004 0 46 0 10 0 002 0 05 B1 0 050 0 004 1 27 0 10 0 002 0 05 C 0 010 0 004 0 25 0 11 0 002 0 05 D 1 650 Typ 1 670 Max 41 91 Typ 42 42 Max E 0 600 0 010 15 24 0 25 E1 0 550 Typ 0 562 Max 13 97 Typ 14 27 Max e1 0 100 0 010 2 54 0 25 L 0 130 0 010 3 30 0 25 α 0 15 0 15 eA 0 655 0 035 16 64 0 89 S 0 090 Max 2 29 Max Notes 1 The maximum value of dimension D includes end flash 2 Dimension E1 does n...

Page 72: ...9P55A K55A 72 Data Sheet Revision History Version Content Date 2 2 Add keyscan description Jan 2011 2 1 Ordering information updated Dec 2008 2 0 Ordering information updated Mar 2008 1 0 Original Jan 2008 ...

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