SH69P55A/K55A
16
5.3. Control of Phase Locked Loop Clock Source (PLL)
A phase locked loop (PLL) is built in SH69P55A/69K55A, which can provide up to 8MHz clock source when the 32.768kHz
oscillator is selected. PLL control register can decide whether PLL enable or disable. When PLL is enabled, PORTC.0 is
shared as PLL capacitor connecting port, which is connected with a RC network. When PLL is disabled, PORTC.0 is shared
as a normal I/O.
PLL Control Register $16
Address Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$16 FS1 FS0 OXS
OXON
R/W
Bit0: Turn on PLL register
Bit1: clock source select (1: PLL, 0: 32.768kHz) register
Bit3 - 2: PLL Frequency select register
X X X 0
R/W Turn
off
PLL
X
X
X
1
R/W Turn on PLL, when 32.768kHz oscillator is selected in code option
X
X
0
X
R/W Clock source is selected as 32.768kHz oscillator
X
X
1
1
R/W Clock source is selected as PLL
0 0 1 1
R/W
PLL provides 8.126MHz clock signal for clock source
(LVR voltage range must be selected as 4V in the code option)
0
1
1
1
R/W PLL provides 4.063MHz clock signal for clock source
1
0
1
1
R/W PLL provides 2.031MHz clock signal for clock source
1
1
1
1
R/W PLL provides 1.016MHz clock signal for clock source
Note:
1. Usage of PLL:
First, configure the FS1 and FS0 in PLL control register.
Second, set OXON = 1 and turn on the PLL.
Third, wait at least 2ms.
Last, set OXS = 1 and select PLL as the system clock source.
2. If LVR voltage range is selected as 2.5V in the code option, the PLL only provides 1, 2, 4MHz clock signal for clock source.
System Register $23
Address Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$23
-
FSTP
-
-
R/W Bit2: 32.768kHz oscillator is closed in the stop
X 1 X X
R/W
32.768kHz oscillator is closed in the stop, if 32.768kHz is selected
in the code option
X 0 X X
R/W
32.768kHz oscillator is not closed in the stop, if 32.768kHz
oscillator is selected in the code option
