SH69P55A/K55A
26
(3) External Trigger Timer Mode
In this mode, the counting is triggered by an external signal via T2 pin (shared with PORTG3). Either the rising or falling edge
can be selected by setting the Timer2 pre-scaler register ($15) T2E (bit3). But the clock source of the up-counter is the
internal system clock. The contents of the Timer2 load register ($384 - $387) are loaded into the up-counter while the highest
nibble ($387) has been written. Only after the Timer2 control register ($27) T2GO (bit3) has been set to 1, a valid edge signal
on the T2 input pin can start counting. The Timer2 interrupt will issue when the up-counter overflows from $FFFF to $0000 if
the Interrupt enable register ($00) IET2 (bit1) is set to 1. When the Timer2 interrupt is generated the up-counter is halted. The
up-counter is restarted by the next valid edge of the T2 pin input.
When the Timer2 control register ($27) DEC (bit2) is set to 1, a valid rising (falling) edge signal on the T2 input pin can start
counting, a valid falling (rising) edge signal on the T2 input pin will stop counting and The contents of the Timer2 load register
($384 - $387) are reloaded into the up-counter. Inputting a proper width pulse can generate interrupts. When the Timer2
control register ($27) DEC (bit2) is cleared to 0, the reverse directive edge input is ignored. The another valid edge input from
T2 pin before the up-counter overflowing is also ignored.
After the Timer2 control register ($27) T2GO (bit3) is set to 1, writing the Timer2 counter register ($384 - $387) can not affect
the up-counter operating anymore. Only when the Timer2 control register ($27) T2GO (bit3) has been cleared to 0, the
contents of the Timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is written.
The T2 pin input signal must follow certain constraints. The system clock samples it in instruction frame cycle. Therefore it is
necessary to be high at least 1/2 t
Timer clock
and low at least 1/2 t
Timer clock
. In this mode, the Timer clock is selected by the
Timer2 pre-scaler register. So, the limitation is applied to the external clock period time (T
E
) described as follows:
T
E
(period time)
≥
1 * t
Timer clock
+ 2 *
∆
T
;
∆
T = 20ns
T
E
(period time)
≥
( M * t
OSC
) + 2 *
∆
T
where M = 2
3
, 2
4
, 2
5
, 2
6
, 2
8
, 2
10
, 2
12
or 2
14
Timer2 Control Register: $27 (under the external trigger timer mode)
Address
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$27 T2GO DEC TM2S1
TM2S0
R/W
Bit1-0: Timer2 mode select register
Bit2: Reverse directive edge input control register
X
0
1
0
R/W Reverse directive edge input is ignored
X
1
1
0
R/W Reverse directive edge input reloads internal up-counter
Timer2 Pre-scaler Register: $15 (under the external trigger timer mode and pulse width measurement mode)
Address
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$15 T2E
T2SC.2
T2SC.1
T2SC.0
R/W
Bit2-0: Timer2 pre-scaler register
Bit3: T2 external signal edge select
X
0
0
0
R/W Timer clock source: f
SYS
/2
12
X
0
0
1
R/W Timer clock source: f
SYS
/2
10
X
0
1
0
R/W Timer clock: source f
SYS
/2
8
X
0
1
1
R/W Timer clock: source f
SYS
/2
6
X
1
0
0
R/W Timer clock source: f
SYS
/2
4
X
1
0
1
R/W Timer clock source: f
SYS
/2
3
X
1
1
0
R/W Timer clock source: f
SYS
/2
2
X
1
1
1
R/W Timer clock source: f
SYS
/2
1
0
X
X
X
R/W T2 input falling edge active (Default)
1
X
X
X
R/W T2 input rising edge active
Timer2 Counter Register: $384 - $387
Address
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$384 T2D.3 T2D.2 T2D.1 T2D.0 R/W
Timer2 load/counter low nibble register
$385 T2D.7 T2D.6 T2D.5 T2D.4 R/W
Timer2
load/counter middle_L nibble register
$386 T2D.11 T2D.10
T2D.9 T2D.8 R/W
Timer2 load/counter middle_H nibble register
$387 T2D.15 T2D.14
T2D.13 T2D.12
R/W
Timer2 load/counter high nibble register
