SH61F83
31
7.2. Interrupt Priorities
Each interrupt source can also be individually programmed to one of the two priority levels by setting or clearing a bit in the
SFR named
IP
(Interrupt Priority) and
IP2
. The Following figure shows the
IP
&
IP2
register in the SH61F83.
Low-priority interrupt can be interrupted by a high-priority interrupt, but cannot be interrupted by another low-priority
interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is
serviced. If interrupt requests the same priority levels are received simultaneously, an internal polling sequence determines
which request is serviced. Thus within each priority level there is a second priority structure determined by the software
polling sequence.
In operation, all the interrupt flags are latched into the interrupt control system every machine cycle. The samples are polled
during the following machine cycle. If the flag for an enabled interrupt is set to 1, the interrupt system generates an LCALL
to the appropriate location in Program Memory, unless some other condition blocks an interrupt, such as an interrupt of
equal or higher priority level already in progress.
The hardware-generated LCALL accesses the contents of the Program Counter pushed onto the stack, and reloads the PC
with the beginning address of the service routine. As previously noted, the service routine for each interrupt begins at a
fixed location.
Only the Program Counter is automatically pushed onto the stack, not the PSW or any other register.
Having only
the PC automatically saved allows the programmer to decide how much time to spend saving other registers.
00B8H
IP
Initial Value
Interrupt Priority Register
Bit7
-
0b
-
Reserved
Bit6
-
0b
-
Reserved
Bit5
-
0b
-
Reserved
Bit4
PTC0
0b
R/W Time Capture0 interrupt priority bit
Bit3
PT1
0b
R/W Base Timer1 interrupt priority bit
Bit2
-
0b
-
Reserved
Bit1
PT0
0b
R/W Base Timer0 interrupt priority bit
Bit0
PEXT0
0b
R/W External interrupt0 priority bit
1: high priority, 0: low priority
Reset Source: Hardware reset or USB reset
00B9H
IP2
Initial Value
Interrupt Priority Register
Bit7
-
0b
-
Not implemented (always 0)
Bit6
PFUN
0b
R/W SUSP/OVL interrupt priority bit
Bit5
PSIE
0b
R/W
SIE interrupt priority bit (NAKT0, NAKR0, NAK1, NAK2, T0_STL, R0_STL,
IN1, IN2)
Bit4
POUT0
0b
R/W Out0 interrupt priority bit
Bit3
PIN0
0b
R/W IN0 interrupt priority bit
Bit2
POT0ERR
0b
R/W OT0ERR interrupt priority bit
Bit1
POWSTUP
0b
R/W OWSTUP interrupt priority bit
Bit0
PSTUP
0b
R/W Setup interrupt priority bit
1: high priority, 0: low priority
Reset Source: Hardware reset or USB reset
