SH61F83
15
5.1.2. Low Voltage Reset (LVR)
(1) Low Voltage Reset 1 (LVR1)
00AFH
PRCON Initial Value
Power-reducing Control Register
Bit[7:3]
-
00000b
-
Reserved
Bit2
ENWDT
0b
R/W
1: Enable Watch-Dog timer under idle mode
0: Disable Watch-Dog timer under idle mode
Reset source: Hardware reset, USB reset, or Resume Reset
Bit1
-
0b
-
Reserved
Bit0
ENLVR1
1b
R/W
1: Enable Low-Voltage Reset 1 under power-down mode
0: Disable Low-Voltage Reset 1 under power-down mode
Reset source: Hardware reset, USB reset, or Resume Reset
The LVR1 circuit will monitor the 1.8V regulator output voltage to the MCU core.
LVR1 reset signal will active when the input power of MCU core was less than V
LVR1
and lasts for T
PW(LVR1)
, LVR1 signal will
end after T
RST(LVR)
when the power was larger than V
LVR1
. See Figure 5-2 for the LVR1 behavior.
T
PW(LVR1)
V
LVR1
GND
V18
MCU_Reset
T
RST(LVR)
Figure 5-2. Low Voltage Reset 1
Note: V
LVR1(min.)
= 1.4V, V
LVR1(typ.)
= 1.5V, and V
LVR1(max.)
= 1.6V
T
PW(LVR1)
(Drop-Down Pulse Width for LVR1) = 2
9
X T
SYS
.
T
RST(LVR)
(Internal Low-voltage Reset Hold Time) = 2
1
6 X T
SYS
.
Under Power-down mode:
-
ENLVR1
= 0: Disable LVR1 under Power-down mode
-
ENLVR1
= 1: Enable LVR1 under Power-down mode
MCU Reset
T
RST(POR)
<T
PW(LVR1)
>T
PW(LVR1)
V
LVR1
GND
Power-down
V18
Figure 5-3. Low Voltage Reset 1 under Power-down Mode
