SH61F83
28
7. Interrupts
7.1. Interrupt Enables
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR named
IE
,
IE2
,
IRQEN
,
IRQEN2
. The register
IE
also contains a global disable bit, which can be cleared to disable all interrupts at once.
Figure 7-1 shows the interrupt register for the SH61F83.
Interrupt Enable Register
00A8H
IE
Initial Value
Interrupt Enable Register
Bit7
EA
0b
R/W
Disable all interrupts.
If EA = 0, no any interrupts will be acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by setting
or clearing its enable bit.
Reset Source: Hardware reset, USB reset or WDT reset
Bit6
-
0b
-
Reserved
Bit5
-
0b
-
Reserved
Bit4
ETC0
0b
R/W Time Capture0 interrupt
Bit3
ET1
0b
R/W Base Timer1 interrupt
Bit2
-
0b
-
Reserved
Bit1
ET0
0b
R/W Base Timer0 interrupt
Bit0
EEXT0
0b
R/W External interrupt0
Enable bit = 1, enables the interrupt
Enable bit = 0, disables the interrupt
Reset source: Hardware reset or USB reset
Note: EA bit will also be clear by WDT reset
00A9H
IE2
Initial Value
Interrupt Enable Register
Bit7
-
0b
-
Reserved
Bit6
EFUN
0b
R/W SUSP/OVL interrupt
Bit5
ESIE
0b
R/W SIE interrupt (NAKT0, NAKR0, NAK1, NAK2, T0STL, R0STL)
Bit4
EOUT0
0b
R/W Out0 interrupt
Bit3
EIN0
0b
R/W IN0 interrupt
Bit2
EOT0ERR
0b
R/W OT0ERR interrupt
Bit1
EOWSTUP
0b
R/W OWSTUP interrupt
Bit0
ESTUP
0b
R/W Setup interrupt
Enable bit = 1, enables the interrupt
Enable bit = 0, disables the interrupt
Reset source: Hardware reset or USB reset
