SIM5218E Hardware Design
SIM5218E_HD_V1.03
11.06.2009
53
t(synca)
PCM_SYNC asserted time
–
–
–
ns
t(syncd)
PCM_SYNC de-asserted time
–
–
–
μ
s
t(clk)
PCM_CLK cycle time
–
–
–
ns
t(clkh)
PCM_CLK high time
–
–
–
ns
t(clkl)
PCM_CLK low time
–
–
–
ns
PCM_SYNC offset time to PCM_CLK falling
–
122
–
ns
1
t(sync_offset)
PCM_SYNC offset time to PCM_CLK falling
–
–
–
ns
t(sudin)
PCM_DIN setup time to PCM_CLK falling
60
–
–
ns
t(hdin)
PCM_DIN hold time after PCM_CLK falling
60
–
–
ns
t(pdout)
Delay from PCM_CLK rising to PCM_DOUT
valid
–
–
60
ns
t(zdout)
Delay from PCM_CLK falling to PCM_DOUT
High-Z
5
–
60 ns
Notes:
1. PCM_SYNC offset time = t(clk)/4.
4 Antenna interface
The RF interface has an impedance of 50
Ω
. To suit the physical design of individual applications
SIM5218E offers two alternatives:
z
Recommended approach: antenna connector on the component side of the PCB
z
Antenna pad and grounding plane placed on the bottom side.
To minimize the loss on the RF cable, it need be very careful to choose RF cable. We recommend
the insertion loss should be meet following requirement:
z
GSM900/GSM850<1dB
z
DCS1800/PCS1900<1.5dB
z
WCDMA 2100<1.5dB
z
WCDMA 1900<1.5dB
z
WCDMA 900<1dB
z
GPS<1dB
4.1 Antenna installation
4.1.1 Antenna connector
SIM5218E use MURATA’s MM9329-2700 RF connector on the module side, we recommend user
use MURATA’s MXTK88XXXXX as matching connector on the application side. Please refer to
appendix for detail info about MURATA’s MXTK88XXXXX.
