SIM5218E Hardware Design
Figure 30
：
SIM5218E to AUX_PCM_CODEC timing
Table 28 :
AUX_CODEC timing parameters
Parameter
Description
Min Typical Max Unit
Note
t(auxsync)
AUX_PCM_SYNC cycle time
–
125
–
μ
s
t(auxsynca) AUX_PCM_SYNC asserted time
–
62.5
–
μ
s
1
t(auxsyncd) AUX_PCM_SYNC de-asserted time
–
62.5
–
μ
s
1
t(auxclk)
AUX_PCM_CLK cycle time
–
7.8
–
μ
s
2
t(auxclkh)
AUX_PCM_CLK high time
–
3.9
–
μ
s
3
t(auxclkl)
AUX_PCM_CLK low time
–
3.9
–
μ
s
3
t(sync_offset) AUX_PCM _SYNC offset time to
AUX_PCM_CLK rising
–
1.95
–
μ
s
4
t(suauxdin) AUX_PCM_DIN setup time to
AUX_PCM_CLK falling
60
–
–
ns
t(hauxdin)
AUX_PCM_DIN hold time after
AUX_PCM_CLK falling
60
–
–
ns
t(pauxdout) Propagation delay from
AUX_PCM_CLK AUX_PCM_DOUT
valid
–
–
60
ns
Note:
1. t(auxsync)/2 ± 10 ns. 2. t(auxclk) = 1/(128 kHz). 3. t(auxclk)/2 ± 10 ns.4. t(auxclk)/4 ± 10 ns.
3.19.2 Primary PCM
The aux codec port also supports 2.048 MHz PCM data and sync timing for
υ
-law codec that
matches the sync timing — this is called the primary PCM interface (or just PCM interface).
User can use AT+CPCM command to change the mode user want.
SIM5218E_ Hardware Design_V1.06
2012.09.21
53
