SIM5218E Hardware Design
Figure 31
：
PRIM_PCM_SYNC timing
Figure 32
：
PRIM_PCM_CODEC to SIM5218E timing
Figure 33
：
SIM5218E to PRIM_PCM_CODEC timing
Table 29 :
PIM_PCM_CODEC timing parameters
Parameter
Description
Min Typical Max Unit
Note
t(sync)
PCM_SYNC cycle time
–
125
–
μ
s
t(synca)
PCM_SYNC asserted time
–
–
–
ns
t(syncd)
PCM_SYNC de-asserted time
–
–
–
μ
s
t(clk)
PCM_CLK cycle time
–
–
–
ns
t(clkh)
PCM_CLK high time
–
–
–
ns
t(clkl)
PCM_CLK low time
–
–
–
ns
PCM_SYNC offset time to PCM_CLK falling
–
122
–
ns
1
t(sync_offset)
PCM_SYNC offset time to PCM_CLK falling
–
–
–
ns
t(sudin)
PCM_DIN setup time to PCM_CLK falling
60
–
–
ns
t(hdin)
PCM_DIN hold time after PCM_CLK falling
60
–
–
ns
t(pdout)
Delay from PCM_CLK rising to PCM_DOUT
–
–
60 ns
SIM5218E_ Hardware Design_V1.06
2012.09.21
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