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Silicon Laboratories SI5351A, Product Manual

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Silicon Laboratories SI5351A Product Manual Download Page 61

Si5351A/B/C

Preliminary Rev. 0.95

61

Reset value = 0000 0000

Reset value = 11xx xxxx

 Register 177. PLL Reset

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

PLLB_RST

PLLA_RST

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit

Name

Function

7

PLLB_RST

PLLB_Reset.

Writing a 1 to this bit will reset PLLB. This is a self clearing bit (Si5351A/C only).

6

Reserved

Leave as default.

5

PLLA_RST

PLLA_Reset. 

Writing a 1 to this bit will reset PLLA. This is a self clearing bit. 

4:0

Reserved

Leave as default.

 Register 183. Crystal Internal Load Capacitance

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

XTAL_CL[1:0]

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit

Name

Function

7:6

XTAL_CL[1:0]

Crystal Load Capacitance Selection. 

These 2 bits determine the internal load capacitance value for the crystal. See "3.1.1. 
Crystal Inputs (XA, XB)" on page 11.
00: Reserved. Do not select this option.
01: Internal CL = 6 pF. 
10: Internal CL = 8 pF. 
11: Internal CL = 10 pF (default). 

5:0

Reserved

Leave as default.

Summary of Contents for SI5351A

Page 1: ...nctional Block Diagram Generates up to 8 non integer related frequencies from 8 kHz to 160 MHz I2 C user definable configuration Exact frequency synthesis at each output 0 ppm error Highly linear VCXO Optional clock input CLKIN Low output period jitter 100 ps pp Configurable spread spectrum selectable at each output Operates from a low cost fixed frequency crystal 25 or 27 MHz Supports static phas...

Page 2: ...Si5351A B C 2 Preliminary Rev 0 95 ...

Page 3: ...cillators and PLLs 19 5 6 Replacing a Crystal with a Clock 20 5 7 HCSL Compatible Outputs 20 6 Design Considerations 21 6 1 Power Supply Decoupling Filtering 21 6 2 Power Supply Sequencing 21 6 3 External Crystal 21 6 4 External Crystal Load Capacitors 21 6 5 Unused Pins 21 6 6 Trace Characteristics 22 7 Register Map Summary 23 8 Register Descriptions 25 9 Si5351A Pin Descriptions 20 Pin QFN 24 Pi...

Page 4: ...rating temperature of 25 C unless otherwise noted VDD and VDDOx can be operated at independent voltages Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time Table 2 DC Characteristics VDD 2 5 V 10 or 3 3 V 10 TA 40 to 85 C Parameter Symbol Test Condition Min Typ Max Unit Core Supply Current IDD Enabled 3 outputs 22 35 mA Enabled 8 outputs 27 45 mA...

Page 5: ... 5 Spread Spectrum Modulation Rate SSMOD 30 31 5 33 kHz VCXO Specifications Si5351B only VCXO Control Voltage Range Vc 0 VDD 2 VDD V VCXO Gain configurable Kv Vc 10 90 of VDD VDD 3 3 V 18 150 ppm V VCXO Control Voltage Linearity KVL Vc 10 90 of VDD 5 5 VCXO Pull Range configurable PR VDD 3 3 V 30 0 240 ppm VCXO Modulation Bandwidth 10 kHz Note Contact Silicon Labs for 2 5 V VCXO operation Table 4 ...

Page 6: ...asured over 10k cycles 30 90 ps pk Cycle to Cycle Jitter VCXO JCC_VCXO 50 95 ps pk RMS Phase Jitter JRMS 12 kHz 20 MHz 3 5 11 ps rms RMS Phase Jitter VCXO JRMS_VCXO 8 5 18 5 ps rms Table 6 Crystal Requirements1 2 Parameter Symbol Min Typ Max Unit Crystal Frequency fXTAL 25 27 MHz Load Capacitance CL 6 12 pF Equivalent Series Resistance rESR 150 Crystal Max Drive Level dL 100 µW Notes 1 Crystals wh...

Page 7: ...DI2C 2 1 8 V 0 0 2 x VDDI2C V Input Current III2C 10 10 10 10 µA Capacitance for Each I O Pin CII2C VIN 0 1 to VDDI2C 4 4 pF I2 C Bus Timeout TTO Timeout Enabled 25 35 25 35 ms Notes 1 Refer to NXP s UM10204 I2 C bus specification and user manual revision 03 for further details go to www nxp com acrobat_download usermanuals UM10204_3 pdf 2 Only I2 C pullup voltages VDDI2C of 2 25 to 3 63 V are sup...

Page 8: ... TJ 55 to 150 C Soldering Temperature Pb free profile 2 TPEAK 260 C Soldering Temperature Time at TPEAK Pb free profile 2 TP 20 40 Sec Notes 1 Permanent device damage may occur if the absolute maximum ratings are exceeded Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet Exposure to absolute maximum rating conditions for extende...

Page 9: ...ultiSynth 0 MultiSynth 1 MultiSynth 2 VDD GND 10 MSOP Si5351A 3 Output R0 R1 CLK0 CLK1 VDDOA R2 R3 CLK2 CLK3 VDDOB R4 R5 CLK4 CLK5 VDDOC R6 R7 CLK6 CLK7 VDDOD MultiSynth 0 MultiSynth 1 MultiSynth 2 MultiSynth 3 MultiSynth 4 MultiSynth 5 MultiSynth 6 MultiSynth 7 VDD GND 20 QFN 24 QSOP SCL A0 SDA Control Logic OEB SSEN I2 C Interface Si5351A 8 Output I2 C Interface PLL B PLL A OSC XA XB ...

Page 10: ... 2 MultiSynth 3 MultiSynth 4 MultiSynth 5 MultiSynth 6 MultiSynth 7 VC VDD GND Si5351B SCL SDA Control Logic OEB SSEN I2 C Interface 20 QFN 24 QSOP R0 R1 CLK0 CLK1 VDDOA R2 R3 CLK2 CLK3 VDDOB R4 R5 CLK4 CLK5 VDDOC R6 R7 CLK6 CLK7 VDDOD MultiSynth 0 MultiSynth 1 MultiSynth 2 MultiSynth 3 MultiSynth 4 MultiSynth 5 MultiSynth 6 MultiSynth 7 VDD GND Si5351C PLL A PLL B XA XB OSC CLKIN SCL SDA Control ...

Page 11: ...ze clocks for multiple clock domains in a design Figure 3 Si5351 Block Diagram 3 1 Input Stage 3 1 1 Crystal Inputs XA XB The Si5351 uses a fixed frequency standard AT cut crystal as a reference to the internal oscillator The output of the oscillator can be used to provide a free running reference to one or both of the PLLs for generating asynchronous clocks The output frequency of the oscillator ...

Page 12: ...lows each of the PLLs to lock to a different source for generating independent free running and synchronous clocks Alternatively both PLLs could lock to the same source The crosspoint switch at the input of the second stage allows any of the MultiSynth dividers to connect to PLLA or PLLB This flexible synthesis architecture allows any of the outputs to generate synchronous or non synchronous clock...

Page 13: ...nable OEB The output enable pin allows enabling or disabling outputs clocks Output clocks are enabled when the OEB pin is held low and disabled when pulled high When disabled the output state is configurable as disabled high disabled low or disabled in high impedance The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading edge after ...

Page 14: ...ndard Mode 100 kbps or Fast Mode 400 kbps and supports burst data transfer with auto address increments The I2C bus consists of a bidirectional serial data line SDA and a serial clock input SCL as shown in Figure 7 Both the SDA and SCL pins must be connected to the VDD supply via an external pull up as recommended by the I2C specification Figure 7 I2C and Control Signals The 7 bit device slave add...

Page 15: ...out is supported for compatibility with SMBus interfaces 1 Read 0 Write A Acknowledge SDALOW N Not Acknowledge SDAHIGH S STARTcondition P STOPcondition Fromslavetomaster Frommaster toslave WriteOperation SingleByte S 0 A RegAddr 7 0 Slv Addr 6 0 A Data 7 0 P A WriteOperation Burst AutoAddressIncrement RegAddr 1 S 0 A RegAddr 7 0 Slv Addr 6 0 A Data 7 0 A Data 7 0 P A 1 Read 0 Write A Acknowledge S...

Page 16: ...nfiguration after power up are made by reading and writing to registers in the RAM space through the I2 C interface A detailed register map is shown in Section 8 Register Descriptions on page 25 5 1 Writing a Custom Configuration to RAM To simplify device configuration Silicon Labs has released the ClockBuilder Desktop The software serves two purposes to configure the Si5351 with optimal configura...

Page 17: ...22 23 0x80 Set interrupt masks see register 2 description Write new configuration to device using the contents of the register map generated by ClockBuilder Desktop This step also powers up the output drivers Registers 15 92 and 149 170 Apply PLLA and PLLB soft reset Reg 177 0xAC Enable desired outputs see Register 3 Use ClockBuilder Desktop v3 1 or later Register Map ...

Page 18: ...ystals and crystal oscillators A 3 output version packaged in a small 10 MSOP is also available for applications that require fewer clocks An example is shown in Figure 13 Figure 13 Using the Si5351A to Replace Multiple Crystals Crystal Oscillators and PLLs 48 MHz USB Controller 28 322 MHz 125 MHz Video Audio Processor 74 25 1 001 MHz 24 576 MHz OSC XA XB CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 PLL Multi Sy...

Page 19: ...nd free running clocks An example is shown in Figure 15 Figure 15 Using the Si5351C to Replace Crystals Crystal Oscillators and PLLs Ethernet PHY USB Controller HDMI Port 28 322 MHz 48 MHz 125 MHz Video Audio Processor 74 25 1 001 MHz 24 576 MHz OSC XA XB CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 PLL VCXO Multi Synth 0 Multi Synth 1 Multi Synth 2 74 25 MHz VC 27 MHz Si5351B Multi Synth 3 Multi Synth 4 Multi S...

Page 20: ...and so on The circuit in the figure below must be applied to each of the two clocks used and one of the clocks in the pair must also be inverted to generate a differential pair See register setting CLKx_INV Figure 17 Si5350C Output is HCSL Compatible Multi Synth N Multi Synth 0 Multi Synth 1 PLLB PLLA XA XB OSC VIN 1 VPP 25 27 MHz Note Float the XB input while driving the XA input with a clock 0 1...

Page 21: ...imum output to output skew is important then all VDDOx must be applied before VDD Unused VDDOx pins should be tied to VDD 6 3 External Crystal The external crystal should be mounted as close to the pins as possible using short PCB traces The XA and XB traces should be kept away from other high speed signal traces See AN551 Crystal Selection Guide for more details 6 4 External Crystal Load Capacito...

Page 22: ...lt It is recommended to configure the trace characteristics as shown in Figure 18 when an output drive setting of 8 mA is used Figure 18 Recommended Trace Characteristics with 8 mA Drive Strength Setting Note Jitter is only specified at 6 and 8 mA drive strength ZO 85 ohms Length No Restrictions CLK Optional resistor for EMI management R 0 ohms ...

Page 23: ...K3_IDRV 1 0 20 CLK4_PDN MS4_INT MS4_SRC CLK4_INV CLK4_SRC 1 0 CLK4_IDRV 1 0 21 CLK5_PDN MS5_INT MS5_SRC CLK5_INV CLK5_SRC 1 0 CLK5_IDRV 1 0 22 CLK6_PDN FBA_INT MS6_SRC CLK6_INV CLK6_SRC 1 0 CLK6_IDRV 1 0 23 CLK7_PDN FBB_INT MS6_SRC CLK7_INV CLK7_SRC 1 0 CLK7_IDRV 1 0 24 CLK3_DIS_STATE CLK2_DIS_STATE CLK1_DIS_STATE CLK0_DIS_STATE 25 CLK7_DIS_STATE CLK6_DIS_STATE CLK5_DIS_STATE CLK4_DIS_STATE 26 41 ...

Page 24: ...5_P3 7 0 84 R5_DIV 2 0 MS5_P1 17 16 85 MS5_P1 15 8 86 MS5_P1 7 0 87 MS5_P3 19 16 MS5_P2 19 16 88 MS5_P2 15 8 89 MS5_P2 7 0 90 MS6_P1 7 0 91 MS7_P1 7 0 92 R7_DIV 2 0 R6_DIV 2 0 93 164 PLL MultiSynth and output clock delay offset Configuration Registers Use ClockBuilder Desktop Software to Determine These Register Values 165 CLK0_PHOFF 7 0 166 CLK1_PHOFF 7 0 167 CLK2_PHOFF 7 0 168 CLK3_PHOFF 7 0 189...

Page 25: ...as specified in Table 4 An interrupt will be triggered INTR pin 0 Si5351C during a LOL condition 0 PLL B is locked 1 PLL B is unlocked When the device is in this state it will trigger an interrupt causing the INTR pin to go low Si5351C only 5 LOL_A PLL A Loss Of Lock Status PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL A loss of lock will occur if the freque...

Page 26: ...igh It remains high until cleared Writing a 0 to this register bit will cause it to clear 0 No PLL B interrupt has occurred since it was last cleared 1 A PLL B interrupt has occurred since it was last cleared 5 LOL_A_STKY PLLA Loss Of Lock Status Sticky Bit The LOL_A_STKY bit is triggered when the LOL_A bit register 0 bit 5 is triggered high It remains high until cleared Writing a 0 to this regist...

Page 27: ...terrupt 6 LOL_B_MASK PLLB Loss Of Lock Status Mask Use this mask bit to prevent the INTR pin Si5351C only from going low when LOL_B is asserted 0 Do not mask the LOL_B interrupt 1 Mask the LOL_B interrupt 5 LOL_A_MASK PLL A Loss Of Lock Status Mask Use this mask bit to prevent the INTR pin Si5351C only from going low when LOL_A is asserted 0 Do not mask the LOL_A interrupt 1 Mask the LOL_A interru...

Page 28: ...CLKx_OEB Output Disable for CLKx Where x 0 1 2 3 4 5 6 7 0 Enable CLKx output 1 Disable CLKx output Register 9 OEB Pin Enable Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name OEB_CLK7 OEB_CLK6 OEB_CLK5 OEB_CLK4 OEB_CLK3 OEB_CLK2 OEB_CLK1 OEB_CLK0 Type R W R W R W R W R W R W R W R W Bit Name Function 7 0 OEB_CLKx OEB pin enable control of CLKx Where x 0 1 2 3 4 5 6 7 0 OEB pin controls enable disable stat...

Page 29: ...served Leave as default 3 PLLB_SRC Input Source Select for PLLB 0 Select the XTAL input as the reference clock for PLLB Si5351A C only 1 Select the CLKIN input as the reference clock for PLLB Si5351C only 2 PLLA_SRC Input Source Select for PLLA 0 Select the XTAL input as the reference clock for PLLA 1 Select the CLKIN input as the reference clock for PLLA Si5351C only 1 0 Reserved Leave as default...

Page 30: ... 1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK0_INV Output Clock 0 Invert 0 Output Clock 0 is not inverted 1 Output Clock 0 is inverted 3 2 CLK0_SRC 1 0 Output Clock 0 Input Source These bits determine the input source for CLK0 00 Select the XTAL as the clock source for CLK0 This option by passes both synthesis stages PLL VCXO MultiSynth and connects CLK0 directly to the osci...

Page 31: ... 1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK1_INV Output Clock 1 Invert 0 Output Clock 1 is not inverted 1 Output Clock 1 is inverted 3 2 CLK1_SRC 1 0 Output Clock 1 Input Source These bits determine the input source for CLK1 00 Select the XTAL as the clock source for CLK1 This option by passes both synthesis stages PLL VCXO MultiSynth and connects CLK1 directly to the osci...

Page 32: ...1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK2_INV Output Clock 2 Invert 0 Output Clock 2 is not inverted 1 Output Clock 2 is inverted 3 2 CLK2_SRC 1 0 Output Clock 2 Input Source These bits determine the input source for CLK2 00 Select the XTAL as the clock source for CLK2 This option by passes both synthesis stages PLL VCXO MultiSynth and connects CLK2 directly to the oscil...

Page 33: ...force MS3 into Integer mode to improve jitter performance Note that the fractional mode is necessary when a delay offset is specified for CLK3 0 MS3 operates in fractional division mode 1 MS3 operates in integer mode 5 MS3_SRC MultiSynth Source Select for CLK3 0 Select PLLA as the source for MultiSynth0 1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK3_INV Output Clock 3 Invert ...

Page 34: ...1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK4_INV Output Clock 4 Invert 0 Output Clock 4 is not inverted 1 Output Clock 4 is inverted 3 2 CLK4_SRC 1 0 Output Clock 4 Input Source These bits determine the input source for CLK4 00 Select the XTAL as the clock source for CLK4 This option by passes both synthe sis stages PLL VCXO MultiSynth and connects CLK4 directly to the osci...

Page 35: ...1 Select PLLB Si5351A C only or VCXO Si5351B only MultiSynth0 4 CLK5_INV Output Clock 5 Invert 0 Output Clock 5 is not inverted 1 Output Clock 5 is inverted 3 2 CLK5_SRC 1 0 Output Clock 5 Input Source These bits determine the input source for CLK5 00 Select the XTAL as the clock source for CLK5 This option by passes both synthe sis stages PLL VCXO MultiSynth and connects CLK5 directly to the osci...

Page 36: ...ock 6 Invert 0 Output Clock 6 is not inverted 1 Output Clock 6 is inverted 3 2 CLK6_SRC 1 0 Output Clock 0 Input Source These bits determine the input source for CLK6 00 Select the XTAL as the clock source for CLK6 This option by passes both synthe sis stages PLL VCXO MultiSynth and connects CLK6 directly to the oscillator which generates an output frequency determined by the XTAL frequency 01 Sel...

Page 37: ...ock 7 Invert 0 Output Clock 7 is not inverted 1 Output Clock 7 is inverted 3 2 CLK7_SRC 1 0 Output Clock 0 Input Source These bits determine the input source for CLK7 00 Select the XTAL as the clock source for CLK7 This option by passes both synthe sis stages PLL VCXO MultiSynth and connects CLK7 directly to the oscillator which generates an output frequency determined by the XTAL frequency 01 Sel...

Page 38: ... when disabled 01 CLKx is set to a HIGH state when disabled 10 CLKx is set to a HIGH IMPEDANCE state when disabled 11 CLKx is NEVER DISABLED Register 25 CLK7 4 Disable State Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CLK7_DIS_STATE CLK6_DIS_STATE CLK5_DIS_STATE CLK4_DIS_STATE Type R W R W R W R W Bit Name Function 7 0 CLKx_DIS_STATE Clock x Disable State Where x 4 5 6 7 These 2 bits determine the state of t...

Page 39: ...ultisynth0 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the MultiSynth0 Divider Register 43 Multisynth0 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS0_P3 7 0 Type R W Bit Name Function 7 0 MS0_P3 7 0 Multisynth0 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the MultiSynth0 Di...

Page 40: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS0_P1 17 16 Multisynth0 Parameter 1 This 18 bit number is an encoded representation of the integer part of the MultiSynth0 divider Register 45 Multisynth0 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS0_P1 15 8 Type R W Bit Name Function 7 0 MS0_P1 15 8 Multisynth0 Parameter 1...

Page 41: ... MS0_P2 19 16 Type R W R W Bit Name Function 7 4 MS0_P3 19 16 Multisynth0 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the MultiSynth0 Divider 3 0 MS0_P2 19 16 Multisynth0 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider Register 48 Multisynth0 Parameters Bit...

Page 42: ...ltiSynth1 Divider Register 50 Multisynth1 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS1_P3 15 8 Type R W Bit Name Function 7 0 MS1_P3 15 8 Multisynth1 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the MultiSynth1 Divider Register 51 Multisynth1 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS1_P3 7 0 Type R W Bit Name Function 7 0 MS1_P3...

Page 43: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS1_P1 17 16 Multisynth1 Parameter 1 This 18 bit number is an encoded representation of the integer part of the MultiSynth1 divider Register 53 Multisynth1 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS1_P1 15 8 Type R W Bit Name Function 7 0 MS1_P1 15 8 Multisynth1 Parameter 1...

Page 44: ... MS1_P2 19 16 Type R W R W Bit Name Function 7 4 MS1_P3 19 16 Multisynth1 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth1 Divider 3 0 MS1_P2 19 16 Multisynth1 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider Register 56 Multisynth1 Parameters Bit...

Page 45: ...ltiSynth1 divider Register 58 Multisynth1 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS1_P3 15 8 Type R W Bit Name Function 7 0 MS1_P3 15 8 Multisynth1 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the MultiSynth1 divider Register 59 Multisynth1 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS1_P3 7 0 Type R W Bit Name Function 7 0 MS1_P3...

Page 46: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS2_P1 17 16 Multisynth2 Parameter 1 This 18 bit number is an encoded representation of the integer part of the Multisynth2 divider Register 61 Multisynth2 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS2_P1 15 8 Type R W Bit Name Function 7 0 MS2_P1 15 8 Multisynth2 Parameter 1...

Page 47: ... MS2_P2 19 16 Type R W R W Bit Name Function 7 4 MS2_P3 19 16 Multisynth2 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth2 divider 3 0 MS2_P2 19 16 Multisynth2 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth2 divider Register 64 Multisynth2 Parameters Bit...

Page 48: ...ltisynth2 divider Register 66 Multisynth3 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS3_P3 15 8 Type R W Bit Name Function 7 0 MS3_P3 15 8 Multisynth3 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth3 divider Register 67 Multisynth3 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS3_P3 7 0 Type R W Bit Name Function 7 0 MS3_P3...

Page 49: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS3_P1 17 16 Multisynth3 Parameter 1 This 18 bit number is an encoded representation of the integer part of the Multisynth3 divider Register 69 Multisynth3 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS3_P1 15 8 Type R W Bit Name Function 7 0 MS3_P1 15 8 Multisynth3 Parameter 1...

Page 50: ... MS3_P2 19 16 Type R W R W Bit Name Function 7 4 MS3_P3 19 16 Multisynth3 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth3 divider 3 0 MS3_P2 19 16 Multisynth3 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth3 divider Register 72 Multisynth3 Parameters Bit...

Page 51: ...ultisynth3 divider Register 74 Multisynth4 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS4_P3 15 8 Type R W Bit Name Function 7 0 MS4_P3 15 8 Multisynth4 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth4 divider Register 75 Multisynth4 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS4_P3 7 0 Type R W Bit Name Function 7 0 MS4_P...

Page 52: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS4_P1 17 16 Multisynth4 Parameter 1 This 18 bit number is an encoded representation of the integer part of the Multisynth4 divider Register 77 Multisynth4 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS4_P1 15 8 Type R W Bit Name Function 7 0 MS4_P1 15 8 Multisynth4 Parameter 1...

Page 53: ... MS4_P2 19 16 Type R W R W Bit Name Function 7 4 MS4_P3 19 16 Multisynth4 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth4 divider 3 0 MS4_P2 19 16 Multisynth4 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth4 divider Register 80 Multisynth4 Parameters Bit...

Page 54: ...ltisynth4 divider Register 82 Multisynth5 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS5_P3 15 8 Type R W Bit Name Function 7 0 MS5_P3 15 8 Multisynth5 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth5 divider Register 83 Multisynth5 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS5_P3 7 0 Type R W Bit Name Function 7 0 MS5_P3...

Page 55: ...0b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 2 Reserved 1 0 MS5_P1 17 16 Multisynth5 Parameter 1 This 18 bit number is an encoded representation of the integer part of the Multisynth5 divider Register 85 Multisynth5 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS5_P1 15 8 Type R W Bit Name Function 7 0 MS5_P1 15 8 Multisynth5 Parameter 1...

Page 56: ... MS5_P2 19 16 Type R W R W Bit Name Function 7 4 MS5_P3 19 16 Multisynth5 Parameter 3 This 20 bit number is an encoded representation of the denominator for the frac tional part of the Multisynth5 divider 3 0 MS5_P2 19 16 Multisynth5 Parameter 2 This 20 bit number is an encoded representation of the numerator for the fractional part of the MultiSynth5 divider Register 88 Multisynth5 Parameters Bit...

Page 57: ...rameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS6_P1 7 0 Type R W Bit Name Function 7 0 MS6_P1 7 0 Multisynth6 Parameter 1 This 8 bit number is the Multisynth6 divide ratio Multisynth6 divide ratio can only be even integers greater than or equal to 6 All other divide values are invalid Register 91 Multisynth7 Parameters Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MS7_P1 7 0 Type R W Bit Name Function 7 0 MS7_P1 ...

Page 58: ...served Leave as default 6 4 R7_DIV 2 0 R7 Output Divider 000b Divide by 1 001b Divide by 2 010b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 3 Reserved Leave as default 1 0 R6_DIV 2 0 R6 Output Divider 000b Divide by 1 001b Divide by 2 010b Divide by 4 011b Divide by 8 100b Divide by 16 101b Divide by 32 110b Divide by 64 111b Divide by 128 ...

Page 59: ...Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CLK1_PHOFF 6 0 Type R W R W R W R W R W R W R W R W Bit Name Function 7 Reserved Only write 0 to this bit 6 0 CLK1_PHOFF 6 0 Clock 1 Initial Phase Offset CLK1_PHOFF 6 0 is an unsigned integer with one LSB equivalent to a time delay of Tvco 4 where Tvco is the period of the VCO PLL associated with this output Register 167 CLK2 Initial Phase Offset Bit D7 D6 D5 D4 D3...

Page 60: ...Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CLK4_PHOFF 6 0 Type R W R W R W R W R W R W R W R W Bit Name Function 7 Reserved Only write 0 to this bit 6 0 CLK4_PHOFF 6 0 Clock 4 Initial Phase Offset CLK4_PHOFF 6 0 is an unsigned integer with one LSB equivalent to a time delay of Tvco 4 where Tvco is the period of the VCO PLL associated with this output Register 170 CLK5 Initial Phase Offset Bit D7 D6 D5 D4 D3...

Page 61: ...A_Reset Writing a 1 to this bit will reset PLLA This is a self clearing bit 4 0 Reserved Leave as default Register 183 Crystal Internal Load Capacitance Bit D7 D6 D5 D4 D3 D2 D1 D0 Name XTAL_CL 1 0 Type R W R W R W R W R W R W R W R W Bit Name Function 7 6 XTAL_CL 1 0 Crystal Load Capacitance Selection These 2 bits determine the internal load capacitance value for the crystal See 3 1 1 Crystal Inp...

Page 62: ...led OEB 7 13 I Output driver enable Low enabled High disabled VDD 20 4 P Core voltage supply pin See 6 2 VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1 See 6 2 VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3 See 6 2 VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5 See 6 2 VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7 See 6 2 GND Center Pad 5 8 17 19 P Groun...

Page 63: ...m enable High enabled Low disabled OEB 7 13 I Output driver enable Low enabled High disabled VDD 20 4 P Core voltage supply pin VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1 See 6 2 VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3 See 6 2 VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5 See 6 2 VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7 See 6 2 GND Cente...

Page 64: ... VDD core with 1 k CLKIN 6 12 I PLL clock input OEB 7 13 I Output driver enable Low enabled High disabled VDD 20 4 P Core voltage supply pin VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1 See 6 2 VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3 See 6 2 VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5 See 6 2 VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7 See ...

Page 65: ...tput clock 2 SCL 4 I Serial clock input for the I2 C bus This pin must be pulled up using a pull up resistor of at least 1 k SDA 5 I O Serial data input for the I2C bus This pin must be pulled up using a pull up resistor of at least 1 k VDD 1 P Core voltage supply pin VDDO 7 P Output voltage supply pin for CLK0 CLK1 and CLK2 See 6 2 Power Supply Sequencing on page 21 GND 8 P Ground Note I Input O ...

Page 66: ... evaluatin of the Si5351A B C The orderable part numbers for the evaluation kits are provided in Figure 20 Figure 20 Si5351A B C Evaluation Kit Si5351X XX A A Product Revision A A Crystal In B Crystal In VCXO C Crystal In CLKIN GT 10 MSOP GM 20 QFN GU 24 QSOP Note The 10 MSOP is only available in the Si5351A variant Si535X EVB XXXXX XXXXX EVB Evaluation Kit 20 QFN 24 QSOP ...

Page 67: ...SC E1 3 81 3 90 3 99 e 0 635 BSC L 0 40 1 27 L2 0 25 BSC q 0 8 aaa 0 10 bbb 0 17 ccc 0 10 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 137 Variation C 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components ...

Page 68: ... 0 50 BSC E 4 00 BSC E2 2 65 2 70 2 75 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 10 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Outline MO 220 variation VGGD 8 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components...

Page 69: ... BSC E1 3 00 BSC e 0 50 BSC L 0 40 0 60 0 80 L2 0 25 BSC q 0 8 aaa 0 20 bbb 0 25 ccc 0 10 ddd 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 137 Variation C 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Compo...

Page 70: ...Added 5 1 Writing a Custom Configuration to RAM on page 16 Added 5 7 HCSL Compatible Outputs on page 20 Added 6 6 Trace Characteristics on page 22 Updated 8 Register Descriptions on page 25 Added register descriptions Revision 0 9 to Revision 0 95 Added 1 8 V VDDO support Updated Table 2 DC Characteristics on page 4 Added soldering profile specs to Table 9 Absolute Maximum Ratings1 on page 8 ...

Page 71: ...Si5351A B C Preliminary Rev 0 95 71 NOTES ...

Page 72: ...ed herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arisi...

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