Table 24:
SiFive PLIC Register Map. Only naturally aligned 32-bit memory accesses are
required.
PLIC Register Map
0x0C00_1004
4B
RO
Last word of pending array
0x0C00_1008
…
Reserved
0x0C00_2000
4B
RW
Start Hart 0 M-Mode inter-
rupt enables
…
0x0C00_2004
4B
RW
End Hart 0 M-Mode interrupt
enables
See Section 10.5 for more
information
0x0C00_2008
…
Reserved
0x0C20_0000
4B
RW
Hart 0 M-Mode priority
threshold
See Section 10.6 for more
information
0x0C20_0004
4B
RW
Hart 0 M-Mode claim/com-
plete
See Section 10.7 for more
information
0x0C20_0008
…
Reserved
0x1000_0000
End of PLIC Memory Map
The FE310-G003 has 52 interrupt sources. These are driven by various on-chip devices as
listed in Table 25. These signals are positive-level triggered.
In the PLIC, as specified in
The RISC‑V Instruction Set Manual, Volume II: Privileged Architec-
ture, Version 1.10
, Global Interrupt ID 0 is defined to mean "no interrupt."
Table 25:
PLIC Interrupt Source Mapping
Source Start
Source End
Source
1
32
GPIO
33
33
UART0
34
34
UART1
Chapter 10 Platform-Level Interrupt Controller (PLIC)
FE310-G003 Manual
© SiFive, Inc.
Page 47