The counter is incremented at a maximum rate determined by the watchdog clock selection.
Each cycle, the counter can be conditionally incremented depending on the existence of certain
conditions, including always incrementing or incrementing only when the processor is not
asleep.
The counter can also be reset to zero depending on certain conditions, such as a successful
write to
wdogfeed
or the counter matching the compare value.
The WDT unit clock,
wdogclk
, is driven by the low-frequency clock
lfclk
. It runs at approxi-
mately 32 kHz.
Watchdog Configuration Register (
wdogcfg: wdog Configuration (
wdogcfg
)
Register Offset
0x0
Bits
Field Name
Attr.
Rst.
Description
[3:0]
wdogscale
RW
X
Counter scale value.
[7:4]
Reserved
8
wdogrsten
RW
0x0
Controls whether the comparator output can set
the wdogrst bit and hence cause a full reset.
9
wdogzerocmp
RW
X
Reset counter to zero after match.
[11:10]
Reserved
12
wdogenalways
RW
0x0
Enable Always - run continuously
13
wdogcoreawake
RW
0x0
Increment the watchdog counter if the processor is
not asleep
[27:14]
Reserved
28
wdogip0
RW
X
Interrupt 0 Pending
[31:29]
Reserved
The
wdogen*
bits control the conditions under which the watchdog counter
wdogcount
is incre-
mented. The
wdogenalways
bit, if set, means the watchdog counter always increments. The
wdogencoreawake
bit, if set, means the watchdog counter increments if the processor core is
not asleep. The WDT uses the
corerst
signal from the wakeup sequencer to know when the
Table 36:
wdogcfg: wdog Configuration
Chapter 13 Watchdog Timer (WDT)
FE310-G003 Manual
© SiFive, Inc.
Page 63