Table 3:
mhpmevent
Register Description
Machine Hardware Performance Monitor Event Register
17
Integer multiplication instruction retired
18
Integer division instruction retired
Microarchitectural Events ,
mhpeventX
[7:0] = 1
Bits
Meaning
8
Load-use interlock
9
Long-latency interlock
10
CSR read interlock
11
Instruction cache/ITIM busy
12
Data cache/DTIM busy
13
Branch direction misprediction
14
Branch/jump target misprediction
15
Pipeline flush from CSR write
16
Pipeline flush from other event
17
Integer multiplication interlock
Memory System Events,
mhpeventX
[7:0] = 2
Bits
Meaning
8
Instruction cache miss
9
Memory-mapped I/O access
Chapter 3 E31 RISC-V Core
FE310-G003 Manual
© SiFive, Inc.
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