Semiconductor Group
Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh
- 7 of 11 -
Parameter
Symbol
Max CPU
= 20
Clock
MHz
Variable
1/2TCL =
CPU Clock
1 to 20 MHz
Unit
min.
max.
min.
max.
WR#/WRH# low time
(with RW-delay)
t12
38+tc
instead of
40+tc
-
2TCL-12+tc
instead of
2TCL -10+tc
-
ns
WR#/WRH# low time
(no RW-delay)
t13
63+tc
instead of
65+tc
-
3TCL-12+tc
instead of
3TCL -10+tc
-
ns
ALE falling edge to
CS#
t38
-7-ta
instead of -
4-ta
10-ta
-7-ta
instead of -
4-ta
10-ta
ns
RDCS#/WRCS# low
time
(with RW-delay)
t48
38+tc
instead of
40+tc
-
2TCL-12+tc
instead of
2TCL -10+tc
-
ns
RDCS#/WRCS# low
time
(with RW-delay)
t49
63+tc
instead of
65+tc
-
3TCL-12+tc
instead of
3TCL -10+tc
-
ns
Notes:
1) Pin READY# has an internal pullup (all C167xx derivatives). This will be documented in the next
revision of the Data Sheet.
2) Timing t28: Parameter description and test changed from ’Address hold after RD#/WR#’ to ’Address
hold after WR#’. It is guaranteed by design that read data are internally latched by the controller before
the address changes.
3) During reset, the internal pullups on P6.[4:0] are active, independent whether the respective pins
are used for CS# function after reset or not.
