Semiconductor Group
Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh
- 3 of 11 -
CPU.17:
Arithmetic Overflow by DIVLU instruction
For specific combinations of the values of the dividend (MDH,MDL) and divisor (Rn), the Overflow (V)
flag in the PSW may not be set for unsigned divide operations, although an overflow occured.
E.g.:
MDH
MDL
Rn
MDH MDL
F0F0
0F0Fh : F0F0h = FFFF FFFFh, but no Overflow indicated !
(result with 32-bit precision: 1 0000h)
The same malfunction appears for the following combinations:
n0n0 0n0n : n0n0
n00n 0nn0 : n00n
n000 000n : n000
n0nn 0nnn : n0nn
where n means any Hex Digit between 8 ... F
i.e. all operand combinations where at least the most significat bit of the dividend (MDH) and the divisor
(Rn) is set.
In the cases where an overflow occurred after DIVLU, but the V flag is not set, the result in MDL is
equal to FFFFh.
Workaround:
Skip execution of DIVLU in case an overflow would occur, and explicitly set V = 1.
E.g.:
CMP Rn, MDH
JMPR cc_ugt, NoOverflow
; no overflow if Rn > MDH
BSET V
; set V = 1 if overflow would occur
JMPR cc_uc, NoDivide ; and skip DIVLU
NoOverflow:
DIVLU Rn
NoDivide:
...
; next instruction, may evaluate correct V flag
Note:
- the KEIL C compiler, run time libraries and operating system RTX166 do not generate or use
instruction sequences where the V flag in the PSW is tested after a DIVLU instruction.
- with the TASKING C166 compiler, for the following intrinsic functions code is generated which uses
the overflow flag for minimizing or maximizing the function result after a division with a DIVLU:
_div_u32u16_u16()
_div_s32u16_s16()
_div_s32u16_s32()
Consequently, an incorrect overflow flag (when clear instead of set) might affect the result of one of the
above intrinsic functions but only in a situation where no correct result could be calculated anyway.
These intrinsics first appeared in version 5.1r1 of the toolchain.
Libraries: not affected
