Siemens SAK-C167CR-L25M Manual Download Page 10

Page: 10 / 11

Semiconductor Group

Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh

- 10 of 11 -

History List

(since device step BA)

Functional Problems

Functional
Problem

Short Description

Fixed in
step

PWRDN.1

Execution of PWRDN Instruction while pin NMI# = high

CPU.8

Jump instruction in EXTEND sequence

CPU.9

PEC Transfers during instruction execution from Internal RAM

CPU.11

Stack Underflow during Restart of Interrupted Multiply

CPU.17

Arithmetic Overflow by DIVLU instruction

RST.1

System Configuration via P0L.0 during Software/Watchdog Timer Reset

RST.3

Bidirectional Hardware Reset

ADC.8

CC31/ADC Interference

ADC.10

Start of Standard Conversion at End of Injected Conversion

ADC.11

Modifications of ADM field while bit ADST = 0

Read Access to XPERs in Visible Mode

X12

P0H spikes after XPER write access and external 8-bit Non-multiplexed bus

PINS.1

OUTPUT Signal Rise Time

AC/DC Deviations

AC/DC
Deviation

Short Description

Fixed in
step

see pages 6 .. 9

Summary of Contents for SAK-C167CR-L25M

Page 1: ...M Data Sheet Addendum 1998 03 User s Manual C167 Derivatives User s Manual V2 0 03 96 Instruction Set Manual 12 97 Version 1 2 Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status ...

Page 2: ... waitstate bit MTTCx 0 is used or b the instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral XRAM CAN and the instructions following the PWRDN instruction are located in external memory In this case the problem will occur for any bus configuration Note the on chip peripherals are still working correctly in particular the Watchdog Timer will reset the device upon...

Page 3: ...ound Skip execution of DIVLU in case an overflow would occur and explicitly set V 1 E g CMP Rn MDH JMPR cc_ugt NoOverflow no overflow if Rn MDH BSET V set V 1 if overflow would occur JMPR cc_uc NoDivide and skip DIVLU NoOverflow DIVLU Rn NoDivide next instruction may evaluate correct V flag Note the KEIL C compiler run time libraries and operating system RTX166 do not generate or use instruction s...

Page 4: ...ffect on the unintended auto scan sequence i e it is not used in this auto scan sequence Note When a conversion is already in progress and then the configuration in register ADCON is changed the new conversion mode in ADM is evaluated after the current conversion the new channel number in ADCH and new status of bit ADST are evaluated after the current conversion when a conversion in fixed channel ...

Page 5: ...ow voltage rises to approx 2 5V spike width approx 7ns 0 2 Vcc P0H x high output high voltage drops to approx 2 0V spike width approx 7ns 0 8 Vcc Referring to a worst case simulation the maximum width of the spikes may be 15ns with full amplitude Vcc Vss But this might not be seen on application level Note that if any of the other bus modes is selected in addition to the 8 bit non multiplexed mode...

Page 6: ...ymbol Limit Values Unit Test short name min max Condition DCVOL 1 Output low voltage Port0 1 4 ALE RD WR WRH BHE CLKOUT RSTOUT VOL 0 45 V IOL 2 0 mA instead of 2 4 mA DCAH 1 ALE active current IALEH 1000 instead of 500 µA VOUT 2 4 V DCRL 1 RD WR active current IRWL 600 instead of 500 µA VOUT VOLmax DCP6L 1 Port 6 active current IP6L 600 instead of 500 µA VOUT VOLmax DCP0L 1 Port 0 configuration cu...

Page 7: ...th RW delay t48 38 tc instead of 40 tc 2TCL 12 tc instead of 2TCL 10 tc ns RDCS WRCS low time with RW delay t49 63 tc instead of 65 tc 3TCL 12 tc instead of 3TCL 10 tc ns Notes 1 Pin READY has an internal pullup all C167xx derivatives This will be documented in the next revision of the Data Sheet 2 Timing t28 Parameter description and test changed from Address hold after RD WR to Address hold afte...

Page 8: ...ad current IOV occurs on analog input channel ANn n 10 than an additional current IAN crosstalk current is caused at the neighbour channels ANn 1 and ANn 1 This behavior causes an additional unadjusted error AUE to the ADC result Relation between IAN and IOV IANn 1 ovf1 IOVn n 10 IANn 1 ovf1 IOVn n 10 2 Overload Current at digital Channel P7 7 A negative overload current IOV at digital Port P7 7 c...

Page 9: ...The overload current crosstalk effect at the analog inputs decreases the analog signal voltage supplied by the analog signal source the crosstalk current flows into the µC In case of a crosstalk current at VAGND in combination with RAGND 40 Ohm the analog signal voltage is increased 5 Calculation Example Assumed system values IOV4 300 µA negative overload current at P5 4 RASRC 20 kOhm resistance o...

Page 10: ...estart of Interrupted Multiply CB CPU 17 Arithmetic Overflow by DIVLU instruction RST 1 System Configuration via P0L 0 during Software Watchdog Timer Reset CB RST 3 Bidirectional Hardware Reset DA ADC 8 CC31 ADC Interference CB ADC 10 Start of Standard Conversion at End of Injected Conversion CB ADC 11 Modifications of ADM field while bit ADST 0 X9 Read Access to XPERs in Visible Mode X12 P0H spik...

Page 11: ...a low level on pin Vpp OWE See also C167CR 4RM Data Sheet 7 97 Bidirectional Reset The C167CR LM CB step and all higher steps allow to indicate an internal watchdog timer or software reset on the RSTIN pin which will be driven low for the duration of the internal reset sequence This option is selectable by software via bit BDRSTEN SYSCON 3 After reset the bidirectional reset option is disabled BDR...

Search results

Summary of Contents for SAK-C167CR-L25M

Reviews:

Related manuals for SAK-C167CR-L25M

Brands by name

Popular brands

Siemens SAK-C167CR-L25M, Manual

Search results

Summary of Contents for SAK-C167CR-L25M

Reviews:

Related manuals for SAK-C167CR-L25M

Brands by name

Popular brands