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PCI Dynamic Bursting
When Enabled, data transfers on the PCI bus, where possible, make use of the high-
performance PCI burst protocol, in which greater amounts of data are transferred at a
single command.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are command with zero wait states.
The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you enable/disable the PCI #2 Access #1 Retry.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By default, two-wait
states are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait
states are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.
PCI Latency Timer (CLK)
The number of clocks programed in the PCI Latency Timer represents the guaranteed
time slice allocated to the 440BX, after which it must complete the current data
transfer phase and surrender the bus as soon as its bus grant is removed.
The PCI Latency Timer is used to guarantee to the PCI agents a minimum amount of
the system resource.
The default setting is 64 PCI clocks.
PCI IRQ Actived By
This item sets the method by which the PCI bus recognize that an IRQ service is
being requested by a device. You should never change the default configuration
unless advised otherwise by your System's manufacturer. Choices are
Level
(default)
and
Edge
.
Assign IRQ For USB
This item allows the user to assign IRQ to on-board USB controller or not.
Since on-board controller is enabled always, if none of IRQ is assigned to it, there
will be a question mark report on system device under windows 95.
Assign IRQ For VGA
This item allows the user to set VGA IRQ Routing table Enabled or Disabled.
