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Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It states that these items should never need to
be altered.
The default settings have been chosen because they provide the best
operating conditions for your system. If you discovered that data was
being lost while using your system, you might consider making any
changes.
DRAM Timing By SPD
This item allows you to select the value in this field, depending on
whether the board using which kind of SDR DRAM.
Ø
The Choice: Enabled or Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
Ø
The Choice: Host CLK, HCLK-33M, HCLK+33M.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
Ø
The Choice: 3, or 2.
