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SDRAM RAS Precharge Time
SDRAM must continually be refreshed or it will lose its data. Nor-
mally, DRAM is refreshed entirely as the result of a single request.
This option allows you to determine the number of CPU clocks allo-
cated for Row Address Strobe to accumulate its charge before the
DRAM is refreshed. If insufficient time is allowed, refresh may be
incomplete and data lost. The options are
Slow
for 3 and
Fast
for 2
CLKs.
DRAM Idle Timer
This item specifies the number of clocks that the DRAM controller will
remain in IDLE state before precharging all pages.
SDRAM CAS latenc
This item defines the CAS Latency timing parameter of the SDRAM
expressed in 66MHz clocks. The options are
2
and
3
CLKs.
SDRAM Precharge
This item Enable/Disable the SDRAM precharge when a page miss
occurs.
DRAM Data Integr
This item allows the user to set DRAM data integrity mode to Non-
ECC or ECC. Non-ECC has byte-wide write capability but no provision
for protecting data integrity in the DRAM array. ECC allows a detec-
tion of single-bit and multiple-bit errors and recovery of single-bit
errors.
System BIOS Cach
This item allows the user to set whether the system BIOS F000~FFFF
areas are cacheable or non-cacheable.
Video BIOS Cacheable
This item allows the user to set whether the video BIOS C000~C7FF
areas are cacheable or non-cacheable.
Video RAM Cacheable
This is a new cache technology for the video memory of the processor.
It can greatly improve the display speed by caching the display data.
You must leave this on the default setting of
Disabled
if your display
card cannot support this feature or else your system may not boot.
