Sharp XV-C1E, Service Manual

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XV-Cl
No. Pin name Connection Function
43 DGND Power. High-voltage power ground (OV).
44 DY 0 Output to TFT panel. TFT panel’s Y-direction shift data output line).
4 5 0 Output to TFT panel. TFT panel’s Y-direction transfer clock output (VDD2 line).
4 6 C L Y 0 Output to TFT panel. TFT panel’s Y-direction transfer clock output (VDD2 line).
4 7 0 Output to TFT panel. TFT panel’s enable signal output (VDD2 line).
48 Power. High-voltage power 2 typical).
49 DGND Power. High-voltage ground (OV).
50 TEST6 I Test terminal input.
51 OE I Output enable control input.
52 NAOUT 0 NAND output.
5 3
I NAND input 2.
5 4 NAND input 1.
55 0
inverted signal output (output to IC).
5 6 F R P 0 1 inverted signal output (output to IC).
57 CSYNC I Composite sync signal input.
58 MVSYNC 0 Vertical sync signal monitor output.
5 9 V L S 0 Output to video circuit.
Video level setting signal output for WIDE mode.
6 0 I lnverter input 2.
61 0
lnverter output
6 2 M F S 0 Field ID signal monitor output.
6 3 V C C P o w e r . Logic circuit power typical).
6 4 G N D P o w e r . Logic circuit power ground (OV).
l
The GND and DGND pins are interconnected inside the chip with a resistor in between. Be sure to keep
both pins at the same potential.
l
When the OE input level gets low, all the output signals to the panel DX, (i thru
CLY, CLY, and come to low level too.
l
Be sure to fix the non-used inverter input and NAND input at the high or low level.
l
Switching between the VIDEO and WIDE modes goes as follows depending on the WMODE and
VMODE input levels. L: Low level, H: High level.
WMODE VMODE Display mode Remarks
NTSC
Intermittent PAL
Letter box (NTSC) VLS: During the period, the black-level video
signal is put into the TFT panel.
l
In the power-saving mode with no display, the thru CLX4 signals are all at low level, whereas the
thru CLX4 signals all at high level.
l
Keep all the test terminal inputs at low level.
l
Keep open the test terminal reference signal outputs and
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