Sharp LS013B7DH07, Technical Literature

Page: 21 / 34

SPEC No.
LD-28204A
MODEL No.
LS013B7DH07
PAGE
19
6-6-2 Data Update Mode (Multiple Lines)
Updates arbitrary multiple lines data. (M0=”Hi”
、
M2
＝
”Lo”)
Gate (n-1)th Line
AG7 D0 AG6
D144
DMY (don
’
t care)
D1 D2
D142 D143
Data writing period
( 144clk )
AG0 AG1
Gate (n)th Line
AG7
D0
D144
D1 D2
D142 D143
DMY (don
’
t care)
Data transfer period
( 8clk [DMY] + 8clk [Address] = 16clk )
Data writing period
( 144clk )
AG6
Data transfer period
( 16clk )
Gate 1st Line
DMY AG7 M0 M1 M2 DMY DMY DMY DMY D0 AG0 AG1 AG2 AG3 AG4 AG5 AG6
D144
DMY (don ’ t care)
D1 D2
D142 D143
Mode selection period
( 3ck+5ckDMY )
Gateline address period
( 8clk )
Data writing period
( 144clk )
Data transfer period
( 8clk [DMY] + 8clk [Address] = 16clk )
SI
SCLK
SCS
Gate (n-1)th Line
AG0 AG1 AG2 AG3
Figure 6-7 Data update mode by Multiple Lines
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “Lo”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “Hi”, outputs VCOM=”Hi”, and when “Lo”, outputs VCOM=”Lo”.
When EXTMODE=”Hi”, it can be “Hi” or “Lo”.
M2: All clear flag.
Refer to 6-6-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “Hi” or “Lo” (“Lo” is recommended.)
※
For gate line address setting, refer to 6-7) Input Signal and Display.
※
Input data continuously.
※
M1: Frame inversion flag is enabled when EXTMODE=
”
Lo
”
.
※
When SCS becomes
“
Lo
”
, M0 and M2 are cleared.
※ Data write period
Data is being stored in 1
st latch block of binary driver on panel.
※
Data transfer period
For example, during GL2nd line data transfer period, GL 2
nd
line address is latched and GL1st
line data is transferred from 1
st
latch to pixel internal memory circuit at the same time.
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