2008-03-14
LC-42SB45U
43
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Supports DDR1-333, DDR1-400, DDR2-400, DDR2-533, DDR2-667
Audio DSP
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Supports Dolby Digital AC-3 decoding (ATSC)
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MPEG-1 layer I/II decoding (DVB)
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Dolby Prologic II
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Audio output: 7.1ch + 2ch (down mix)
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Pink noise and white noise generator
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Equalizer
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Bass management
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3D surround processing with virtual surround
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Audio and video lip synchronization
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Supports reverberation
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Automatic volume control
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One SPDIF out
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The MT5382AR supports 5-bit (10-channel) main audio I2S output interface. Each channel is up to 24-bit
resolution.
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While internal audio DAC is disabled, the MT5382AR supports 1-bit (2-channel) aux audio I2S output I/F.
Each channel is up to 24-bit resolution.
Digital TV Demodulator
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Compliant with ATSC digital television standard
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Supports SCTE DVS-031 and ITU J.83 Annex B digital CATV standard
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Accepts direct IF (44 MHz or 43.75 MHz) and low IF (5.38 MHz)
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NTSC interference rejection capability
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Passes all Brazil fading channel ensembles
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Meets all ATSC/A74 requirements
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Excellent adjacent and co-channel rejection capability, only a single SAW is required
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Dual digital AGC controls for IF and RF, respectively
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Full-digital frequency offset recovery with wide acquisition range
±
1 MHz for ATSC and
±
250 kHz for
CATV reception
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EIA/CEA-909 antenna interface, both mode A, and mode B are supported
Analog TV IF Demodulator
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Supports NTSC M/N standard
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Accepts IF frequency at 45.75 MHz
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Full digital AGC control and carrier recovery
Periopherals
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MT5382 AR has two built-in dedicated UARTs with TxFIFO and one shared UART,one of them has hardware flow control and high speed data
transferring
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The MT5382AR has three basic serial interfaces;one is for the tuner ,one is the master for general purpose and the other is the slave for HDMI EDID
data.The MT5382AR has two extra slave serial interfaces used for the second and the third HDMI EDID data
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Three PWMs
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The MT5382AR supports up to 2 serial flash or 1 serial flash + 1 NAND flash.
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While NAND Flash is not enabled, the MT5382 AR supports xD/SM, MS/MS-PRO, SD/MMC, and SDHC
card reader.
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IR blaster and receiver
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Real-time clock and watchdog controller
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1-port USB2.0/1.1 host supports USB mass storage class devices.
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Supports five servo ADCs.
IC Outline
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The MT5382AR is 465-pin BGA package.
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3.3V/1.0V and 2.5V for DDR1,1.5V for DDR2.
Summary of Contents for AQUOS LC-42SB45U
Page 6: ...LC 42SB45U 6 TV Front view TV Rear view ...
Page 11: ...2008 03 14 LC 42SB45U 11 3 DIMENSIONS ...
Page 50: ...LC 42SB45U 50 3 2 U102 LP2996MRX PSOP 8 3 2 1 Pin Connections and short description ...
Page 54: ...LC 42SB45U 54 3 8 U402 MX25L3205DMI 12G SOP 16 3 8 1 Block Diagram ...
Page 55: ...2008 03 14 LC 42SB45U 55 3 8 2 PIN CONFIGURATION ...
Page 56: ...LC 42SB45U 56 CHAPTER 6 BLOCK DIAGRAM WIRING DIAGRAM 1 MT5382 POWER MAGAGEMENT BLOCK DIAGRAM ...
Page 57: ...2008 03 14 LC 42SB45U 57 2 MAIN BOARD BLOCK DIAGRAM ...
Page 58: ...LC 42SB45U 58 3 WIRING DIAGRAM ...
Page 60: ...60 LC 42SB45U MAIN Unit Side B ...
Page 61: ...LC 42SB45U 1 POWER UNIT PRINTED WIRING BOARD POWER Unit Side A 61 ...
Page 62: ...LC 42SB45U POWER Unit Side B 62 ...
Page 64: ...64 LC 42SB45U IR Unit Side A 3 IR UNIT PRINTED WIRING BOARD IR Unit Side A Cn001 A2 ...