SM-C93
SM-C93 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R - Reviewed by M.B. - Copyright © 2021 SECO S.p.A.
35
3.2.1.4
DP++ interface signals
As described in the previous paragraph, the Intel
®
family of SOCs formerly coded as Elkhart Lake offers a native multimode Display Port (DP) interface, with a resolution
up to 4096 x 2160 @60Hz
The signals related to DP++ are as follows:
DP/ DP0_LANE0-: DP Channel #0 differential data pair #0.
DP/ DP0_LANE1-: DP Channel #0 differential data pair #1.
DP/ DP0_LANE2-: DP Channel #0 differential data pair #2.
DP/ DP0_LANE3-: DP Channel #0 differential data pair #3.
DP0_HPD: Hot Plug Detect, Active high Input signal of +1.8V_RUN electrical level from carrier board. 1M
Ω
pull-down resistor is placed on module for this signal.
: DDC Clock line for DP Channel #0. Bidirectional signal, +3.3
-up resistor
DP0_AUX-: DDC Data line for DP Channel #0. Bidirectional signal, +3.3
-up resistor
DP0_AUX_SEL: Select input signal to switch between I2C Clock/Data for HDMI (high level) and Display Port Auxiliary Channel for DP/HDMI (low level). 1M
Ω
pull-
down resistor is placed on module for this signal.
Please refer to the following schematics as an example of connection of DP interface on the carrier board, with Voltage clamping diodes highly recommended on all
