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SM-C93

SM-C93 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R - Reviewed by M.B. - Copyright © 2021 SECO S.p.A.

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The signals for Channel #1 are LVDS, when this interface is selected in factory board configuration, otherwise these pins will be not connected.

/ LVDS1_0- : LVDS Channel #1 differential data pair #0
/ LVDS1_1-: LVDS Channel #1 differential data pair #1
/LVDS1_2-: LVDS Channel #1 differential data pair #2
/ LVDS1_3-: LVDS Channel #1 differential data pair #3
L/ LVDS1_CK-: LVDS Channel #1 differential Clock

Please refer to the following schematics as an example of connection of dual channel LVDS interface on the carrier board, with EMI filtering section included.

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Summary of Contents for Smarc SM-C93

Page 1: ...SM C93 SMARC Rel 2 1 1 compliant module with the Intel Atom x6000E Series and Intel Pentium and Celeron N and J Series processors formerly Elkhart Lake for FuSa applications...

Page 2: ...s been made to ensure the accuracy of this manual However SECO S p A accepts no responsibility for any inaccuracies errors or omissions herein SECO S p A reserves the right to change precise specifica...

Page 3: ...1 6 RoHS compliance 7 1 7 Terminology and definitions 8 1 8 Reference specifications 11 OVERVIEW 13 2 1 Introduction 14 2 2 Technical Specifications 15 2 3 Electrical Specifications 17 2 3 1 Power Co...

Page 4: ...ition 1 0 Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 4 Warranty Information and assistance RMA number request Safety Electrostatic Discharges RoHS compliance Terminology and...

Page 5: ...ne The RMA authorisation number must be put both on the packaging and on the documents shipped with the items which must include all the accessories in their original packaging with no signs of damage...

Page 6: ...ter it is possible to send the faulty product to the SECO Repair Centre In this case follow this procedure o Returned items must be accompanied by a RMA Number Items sent without the RMA number will b...

Page 7: ...ng RoHS compliant components and is manufactured on a lead free production line It is therefore fully RoHS compliant Always switch the power off and unplug the power supply unit before handling the bo...

Page 8: ...video display interface developed especially for internal connections between boards and digital displays GBE Gigabit Ethernet Gbps Gigabits per second GND Ground GPI O General purpose Input Output HE...

Page 9: ...chnology Attachment a differential full duplex serial interface for Hard Disks SD Secure Digital a memory card type SDIO Secure Digital Input Output an evolution of the SD standard that allows the use...

Page 10: ...USB Universal Serial Bus VP8 Open video compression format a traditional block based transform coding format VP9 Successor to VP8 customized for video greater than 1080p WMV9 Series 9 of Windows Media...

Page 11: ...c us en documents product specifications high definition audio specification pdf HDMI http www hdmi org index aspx I2C http www nxp com documents other UM10204_v5 pdf I2S https www sparkfun com datash...

Page 12: ...2 SDIO https www sdcard org developers overview sdio SM Bus http www smbus org specs TMDS http www siliconimage com technologies tmds UEFI http www uefi org USB 2 0 and USB OTG http www usb org develo...

Page 13: ...Rev First Edition 1 0 Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 13 Introduction Technical Specifications Electrical Specifications Mechanical Specifications Supported Opera...

Page 14: ...ties of combining with a ready to use carrier board like the SECO CSM B79 or customised carrier board The Embedded Memory Controller allows the integration of up to 16GB of LPDDR4 Memory directly sold...

Page 15: ...Computing Memory 32 bit LPDDR4x Soldered Down Memory Up to 16GB Quad Channel with In Band Error Correction Code IBECC Safety Related feature supported 4GB Dual Channel 8GB or 16GB Quad Channel Speed...

Page 16: ...and ISO 13849 Power supply voltage 5VDC and 3 3V_RTC Operating System Microsoft Windows 10 Enterprise 64 bit Linux Yocto 64 bit Operating temperature Commercial version 0 C 60 C Industrial version 40...

Page 17: ...ition Status Configuration 16GB LPDDR4 128GB eMMC 4 x PCI e LVDS and 2x DP TPM 2 0 Comm Temp Range Intel Pentium J6425 8GB LPDDR4 128GB eMMC 4 x PCI e LVDS and 2x DP TPM 2 0 Comm Temp Range Intel RE 1...

Page 18: ...g meaning VDD_IN Module power input voltage 5V voltage directly coming from the card edge connector internally named as 5V_DSW VDD_RTC Low current RTC circuit backup power 3V coin cell voltage coming...

Page 19: ...o SMARC specifications components placed on bottom side of SM C93 will have a maximum height of 1 3mm Keep this value in mind when choosing the MXM connector s height if there is the need to place com...

Page 20: ...USB 2 0 PCI e A C eMMC 1x SDIO 2x DP eDP LVDS Ch B LVDS Ch A GP_I2C Not Safety Related features Safety Status HW Power Sequencing Voltage Supervisors 1x RGMII Safety Related Black Channel features 1x...

Page 21: ...SM C93 SM C93 User Manual Rev First Edition 1 0 Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 21 Introduction Connectors description...

Page 22: ...t 2021 SECO S p A 22 3 1 Introduction According to SMARC specifications all interfaces to the board are available through a single card edge connector TOP SIDE BOTTOM SIDE Card Edge golden finger pin...

Page 23: ...1 are implemented on card edge connector therefore please refer to the following table for a list of effective signals reported on the card edge connector For accurate signals description please consu...

Page 24: ...P28 S29 SERDES_0_TX PCIE_D_TX O SERDES PCI e GBE I O GBE0_MDI0 P29 S30 SERDES_0_TX PCIE_D_TX O SERDES PCI e GBE I O GBE0_MDI0 P30 S31 GBE1_LINK_ACT O GBE N C P31 S32 SERDES_0_RX PCIE_D_RX I SERDES PC...

Page 25: ...I O USB SPI 1 eSPI INTERFACE SPI1_CS1 ESPI_CS1 P55 S56 ESPI_IO_2 I O eSPI INTERFACE SPI 1 eSPI INTERFACE O SPI1_CK ESPI_CK P56 S57 ESPI_IO_3 I O eSPI INTERFACE SPI 1 eSPI INTERFACE I O SPI1_DIN ESPI_...

Page 26: ...E_A_RX P86 S87 PCIE_B_RX I PCI e PCI e I PCIE_A_RX P87 S88 PCIE_B_RX I PCI e GND P88 S89 GND PCI e O PCIE_A_TX P89 S90 PCIE_B_TX O PCI e PCI e O PCIE_A_TX P90 S91 PCIE_B_TX O PCI e GND P91 S92 GND DP...

Page 27: ...FUSA I O GPIO8 CHX_RLYSWITCH P116 S117 LVDS1_2 O PRIMARY_DISPLAY GPIO FUSA I O GPIO9 CHXOKNOX0 P117 S118 LVDS1_2 O PRIMARY_DISPLAY GPIO FUSA I O GPIO10 CHXOKNOK1 P118 S119 GND GPIO FUSA I O GPIO11 SPI...

Page 28: ...RIAL O SER3_TX P140 S141 LCD0_BKLT_PWM O LCD_SUPPORT ASYNC_SERIAL I SER3_RX P141 S142 GPIO12 SPIM_SCLK I O GPIO FUSA GND P142 S143 GND CAN O CAN0_TX P143 S144 eDP0_HPD I PRIMARY_DISPLAY CAN I CAN0_RX...

Page 29: ...g Pulse Width Modulated PWM regulations 1 8V_RUN electrical level Output I2C_LCD_DAT LCD I2C Data This signal is used to read the LCD display EDID EEPROM 1 8V_RUN electrical level with a 2 2k pull up...

Page 30: ...ly supported by the SOC For this reason considering that LVDS dual channel interfaces can be factory alternative on the same pins with eDP interface on SM C93 module can be implemented an eDP to LVDS...

Page 31: ...ifferential Clock OR the signals for Channel 0 are eDP eDP0_TX0 eDP0_TX0 eDP Channel 0 differential data pair 0 eDP0_TX1 eDP0_TX1 eDP Channel 0 differential data pair 1 eDP0_TX2 eDP0_TX2 eDP Channel 0...

Page 32: ...not connected LVDS1_1 LVDS1_0 LVDS Channel 1 differential data pair 0 LVDS1_1 LVDS1_1 LVDS Channel 1 differential data pair 1 LVDS1_2 LVDS1_2 LVDS Channel 1 differential data pair 2 LVDS1_3 LVDS1_3 L...

Page 33: ...LY ONE set of signals from the following two sets are present dependent on the factory board configuration EITHER the signals for the Channel are HDMI HDMI_D0 HDMI_D0 HDMI Output Differential Pair 0 H...

Page 34: ...tput Differential Pair 3 DP1_AUX DDC Clock line for DP Channel 1 Bidirectional signal 3 3 up resistor DP1_AUX DDC Data line for DP Channel 1 Bidirectional signal 3 3 up resistor DP1_HPD Hot Plug Detec...

Page 35: ...data pair 2 DP0_LANE3 DP0_LANE3 DP Channel 0 differential data pair 3 DP0_HPD Hot Plug Detect Active high Input signal of 1 8V_RUN electrical level from carrier board 1M pull down resistor is placed...

Page 36: ...al ATA Channel 1 Transmit differential pair SATA_RX SATA_RX Serial ATA Channel 1 Receive differential pair SATA_ACT Serial ATA Activity Led Active low output signal at 3 3V_RUN voltage 10nF AC series...

Page 37: ...o send command from Host Intel processor to the connected card and to send the response from the card to the Host SDIO_CD Card Detect Input Active Low Signal electrical level 3 3V_RUN up resistor This...

Page 38: ...signal Electrical level 1 8V_ALW SPI1_CK SPI channel 1 ALW SPI1_DIN SPI0 channel 1 Master Data Input electrical level 1 8V_ALW SPI1_DO SPI0 channel 1 Master Data Output electrical level 1 8V_ALW OR t...

Page 39: ...HDA_SDO Digital audio Output Output from the module to the Carrier board electrical level 1 8V_RUN HDA_SDI Digital audio Input Input from the module to the Carrier board electrical level 1 8V_RUN HDA...

Page 40: ...aged by Intel processor SER1_RX HS UART 0 Interface Serial data Receive input line 1 8V_ RUN electrical level It is directly managed by Intel processor SER2_TX UART 1 Interface Serial data Transmit ou...

Page 41: ...Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 41 In the following schematic here is an example of UART interface on the carrier board with a multiprotocol transceiver allowing...

Page 42: ...resistor Refer to SMARC 2 1 Specification for OC operation information USB2 USB2 Universal Serial Bus Port 2 0 2 differential pair USB2_EN_OC Power Enable and up resistor Refer to SMARC 2 1 Specificat...

Page 43: ...ess lane 0 Receiving Input Differential pair PCIE_A_TX PCIE_A_TX PCI Express lane 0 Transmitting Output Differential pair PCIE_A_REFCK PCIE_A_REFCK PCI Express Reference Clock for lane 0 Differential...

Page 44: ...IE_C_TX PCI Express lane 2 Transmitting Output Differential pair PCIE_C_REFCK PCIE_C_REFCK PCI Express Reference Clock for lane 2 Differential Pair PCIE_C_RST Reset Signal that is sent from SMARC Modu...

Page 45: ...Dependent Interface MDI Transmit differential pair GBE0_LINK_ACT Ethernet controller activity indicator Active Low Output signal 3 3V_ALW electrical level GBE0_LINK100 Ethernet controller 100Mbps lin...

Page 46: ...t Ethernet interfaces 3 2 1 15 CAN interface signals Two CAN interfaces directly managed by the Elkhart Lake processor are available on SMARC card edge connector CAN0_TX CAN Transmit Output for CAN Bu...

Page 47: ...al level GPIO13 General Purpose I O 13 1 8V_DSW electrical level 3 2 1 18 FuSa signals As a factory alternative to GPIO signals SM C93 does provide functional safety functions through following signal...

Page 48: ...at the processor has reached its maximum safe operating temperature Active high signal 3 3V_ RUN electrical level up resistor FUSA_PWRFAIL FuSa Power Fail indication output signal Active low signal 3...

Page 49: ...ific test function s Input active low signal 1 8V_DSW electrical level with a 10k pull up resistor At the moment this function is not implemented and reserved for its use in the future SMB_ALERT_1V8 S...

Page 50: ...SM C93 SM C93 User Manual Rev First Edition 1 0 Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 50 Thermal Design...

Page 51: ...e module It is an absolute requirement that the customer after thorough evaluation of the processor s workload in the actual system application the system enclosure and consequent air flow Thermal ana...

Page 52: ...M C93 User Manual Rev First Edition 1 0 Last Edition 1 0 Author A R Reviewed by M B Copyright 2021 SECO S p A 52 SECO S p A Via A Grandi 20 52100 Arezzo ITALY Ph 39 0575 26979 Fax 39 0575 350210 www s...

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