Sanyo PDG-DHT8000L - 8000 Lumens, Service Manual

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Electrical Adjustment
Grp / No. Item Function Range Initial Note
80 FPGA_NIOS
0 Demo On/Off Demo Mode On/Off (1:ON,0:Off) 0 - 1 0
1 Demo Mode Demo Mode Swith (0:Demo0,1:Demo1...) 0 - 7 0
2 Area Big Chg 0 - 4095 67
3 Area Small Chg 0 - 4095 67
4 Area Chg Sens 0 - 4095 150
5 UV_DLT 0 - 31 3
6 UV_GAIN 0 - 2047 1030
7 UV_SFT 0 - 32767 6180
8 Y Range Brightness (Y) Range 0 - 31 8
9 Hue Range Hue Range 0 - 30 15
10 Gain Range Hue Gain Range (1/100) 0 - 50 30
11 GM_Min Slope Gamma Min. Slope (1/10) 0 - 10 3
12 GM_Max Slope Gamma Max Slope (1/10) 10 - 30 18
13 GM_Converge Gamma Converge Point 1 - 5 3
14 Same Hue Same Hue Range on Color Correction 1 - 10 3
15 Cur_UV Norm Min. UV Norm on Color Correction 0 - 255 5
16 Cur_Min Y Min. Brightness on Color Correction 0 - 255 0
17 Cur_Max Y Max Brightness on Color Correction 0 - 255 255
18 Same_Y Same Brightness Range on Color Correction 0 - 63 24
19 Conv_Y Converge Brightness Range on Color Correction 0 - 127 64
20 WB_Limit 0 WB Correction Limit Point 0 [Black] 0 - 255 4
21 WB_Limit 1 WB Correction Limit Point 1 0 - 255 4
22 WB_Limit 2 WB Correction Limit Point 2 0 - 255 6
23 WB_Limit 3 WB Correction Limit Point 3 0 - 255 7
24 WB_Limit 4 WB Correction Limit Point 4 0 - 255 9
25 WB_Limit 8 WB Correction Limit Point 8 [White] 0 - 255 16
26 WB_Limit In WB Correction Limit In (WB_Limit In < WB_Limit Out) 0 - 255 8
27 WB_Limit Out WB Correction Limit Out (WB_Limit In < WB_Limit Out) 0 - 255 16
28 BKMOD
0:Blending Mode (NORMAL) 4 Video Overlap Disable
1:Blending Mode (BLANKING) 4 Video Overlap Disable
2:Blending Mode (NORMAL) 4 Video Overlap Enable
3:Blending Mode (BLANKING) 4 Video Overlap Enable
0 - 3 2
29
BLD_I_SIZE_H
Blending : Inner Frame Width H 0 - 255 10
30 BLD_I_SIZE_V Blending : Inner Frame Width V 0 - 255 10
31 BLD_CURVE Blending : CURVE 0 - 255 0
32 RGB_GAIN_4SEG_BCON_DYNAMIC Blending : RGB_GAIN (4SEG,BC ON,Dynamic) 0 - 511 256
33
RGB_GAIN_4SEG_BCON_STANDARD
Blending : RGB_GAIN (4SEG,BC ON,Standard) 0 - 511 256
34 RGB_GAIN_4SEG_BCON_CINEMA Blending : RGB_GAIN (4SEG,BC ON,Cinema) 0 - 511 256
35 RGB_GAIN_4SEG_BCON_REAL Blending : RGB_GAIN (4SEG,BC ON,Real) 0 - 511 256
36 RGB_GAIN_4SEG_BCON_DICOM Blending : RGB_GAIN (4SEG,BC ON,Dicom) 0 - 511 256
37
RGB_GAIN_4SEG_BCOFF_DYNAMIC
Blending : RGB_GAIN (4SEG,BC OFF,Dynamic) 0 - 511 256
38 RGB_GAIN_4SEG_BCOFF_STANDARD Blending : RGB_GAIN (4SEG,BC OFF,Standard) 0 - 511 256
39 RGB_GAIN_4SEG_BCOFF_CINEMA Blending : RGB_GAIN (4SEG,BC OFF,Cinema) 0 - 511 256
40 RGB_GAIN_4SEG_BCOFF_REAL Blending : RGB_GAIN (4SEG,BC OFF,Real) 0 - 511 256
41
RGB_GAIN_4SEG_BCOFF_DICOM
Blending : RGB_GAIN (4SEG,BC OFF,Dicom) 0 - 511 256
42 RGB_GAIN_6SEG_BCON_DYNAMIC Blending : RGB_GAIN (6SEG,BC ON,Dynamic) 0 - 511 256
43 RGB_GAIN_6SEG_BCON_STANDARD Blending : RGB_GAIN (6SEG,BC ON,Standard) 0 - 511 256
44 RGB_GAIN_6SEG_BCON_CINEMA Blending : RGB_GAIN (6SEG,BC ON,Cinema) 0 - 511 256
45
RGB_GAIN_6SEG_BCON_REAL
Blending : RGB_GAIN (6SEG,BC ON,Real) 0 - 511 256
46 RGB_GAIN_6SEG_BCON_DICOM Blending : RGB_GAIN (6SEG,BC ON,Dicom) 0 - 511 256
47 RGB_GAIN_6SEG_BCOFF_DYNAMIC Blending : RGB_GAIN (6SEG,BC OFF,Dynamic) 0 - 511 256
48 RGB_GAIN_6SEG_BCOFF_STANDARD Blending : RGB_GAIN (6SEG,BC OFF,Standard) 0 - 511 256
49
RGB_GAIN_6SEG_BCOFF_CINEMA
Blending : RGB_GAIN (6SEG,BC OFF,Cinema) 0 - 511 256
50 RGB_GAIN_6SEG_BCOFF_REAL Blending : RGB_GAIN (6SEG,BC OFF,Real) 0 - 511 256
51 RGB_GAIN_6SEG_BCOFF_DICOM Blending : RGB_GAIN (6SEG,BC OFF,Dicom) 0 - 511 256
81 FPGA_MOTHER
1 PC-Dot Clock Rate Slot - Digital Dot Clock Rate for PC 900 - 1100 1002
2 AV-Dot Clock Rate Slot - Digital Dot Clock Rate for AV 900 - 1100 1002
82 FPGA_MOTHER (Slot,Card)
0 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase [DVI-Dsub] 0 - 7 5
1 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase [HDCP-DVI] 0 - 7 5
2 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase [Dual-SDI] 0 - 7 5
3 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase [AMIMON] 0 - 7 5
4 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase [Warp & Blending] 0 - 7 5
5 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase (Reserved) 0 - 7 0
6 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase (Reserved) 0 - 7 0
7 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase (Reserved) 0 - 7 0
8 SIG_DLY_AJY (EXT. SLOT1) EXT. SLOT1 Clock Phase (Reserved) 0 - 7 0