S&T Kontron SDML-WLU0 Series, User Manual

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SDML-WLU0 Series - User Guide, Rev. 1.0
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Pin Key E CNVi Note
Signal Description Signal Description
24 Key Key
25 Key Key
26 Key Key
27 Key Key
28 Key Key
29 Key Key
30 Key Key
31 Key Key
32 UART_TX UART data output RGI_DT RGI bus Tx
33 GND Ground GND Ground
34 UART_CTS UART clear to send RGI_RSP RGI bus Rx
35 PET0+ PCIe Lane 0 Tx pair (+) -
36 UART_RTS UART request to send BRI_DT BRI bus Tx
37 PET0- PCIe Lane 0 Tx pair (-) -
38 Clink_RST Wi-Fi CLINK host bus reset -
39 GND Ground GND Ground
40 Clink_DATA Wi-Fi CLINK host bus data -
41 PER0+ PCIe Lane 0 Rx pair (+) -
42 Clink_CLK Wi-Fi CLINK host bus clock -
43 PER0- PCIe Lane 0 Rx pair (-) -
44 - -
45 GND Ground GND Ground
46 - -
47 PCIe reference clock pair (+) -
48 - -
49 REFCLK0- PCIe reference clock pair (-) -
50 SUSCLK 32.768 kHz clock supply input SUSCLK 32.768 kHz clock supply input
51 GND Ground GND Ground
52 PERST0# PCIe reset -
53 CLKREQ0# Reference clock request signal -
54 W_DISABLE2# Wireless disable 2 W_DISABLE2# Wireless disable 2
55 PEWAKE0# PCIe wake -
56 W_DISABLE1# Wireless disable 1 W_DISABLE1# Wireless disable 1
57 GND Ground GND Ground
58 - -
59 - WT_D1N CNVio bus Tx Lane 1 (-)
60 - -
61 - WT_D1P CNVio bus Tx Lane 1 (+)
62 - -
63 GND Ground GND Ground
64 - REFCLK0 Reference clock