SDML-WLU0 Series - User Guide, Rev. 1.0
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Connector Locations
4.1.
Top Side
Figure 2: Top Side
Table 8: Jumper List
Item
Designation
Description
See Chapter
1
JP1
MFG Mode Selection
7.12.1
2
JP3
USB Power Selection
7.12.2
3
JP4
M.2 Key B Lane 0 Selection
7.12.3
4
JP5
Flash Descriptor Security Override Selection
7.12.4
5
JP6
AT / ATX Power Mode Selection
7.12.5
6
JP7
Clear CMOS Selection
7.12.6
Table 9: Top Side Internal Connector Pin Assignment
Item
Designation
Description
See Chapter
7
CN18
RTC Power Input Wafer
7.2
8
CN1
FAN Wafer
7.3
9
CN2
Micro SIM Card Holder for M2B1
7.10
10
CN3
P80 Header LPC
7.5
11
CN4
SPI 10-pin Header
7.6
12
CN5
Activity Indicator Header for M2E1
7.11
13
CN8
USB 2.0 Port 8 & 9
7.4
14
CN9
Activity Indicator Header for M2B1
7.11
15
DIMM1
DDR4 Channel 0 SO-DIMM Slot
3.6
1
2 3 12
4
5
6
8
9
10
11
13
14
15
16
17
18
7
19 20
b
a
c
d