S&T Kontron COMe-bTL6, User Manual, Page: 90 / 101

COMe-bTL6 - User Guide. Rev. 1.5
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Function Second level Sub-Screen/Description
Serial IO
Configuration>
SPI0 Controller
&
SPI1 Controller UART0 (00:30:00) cannot be disabled when child
device is enabled like CNVi Bluetooth
(\_SB.PC00.UA00.BTH=)
UART0 (00:30:00) cannot be enabled when I2S
Audio codec is enabled (\SB.PC00.I2C0.HDAC)
[Enabled, Disabled]
UART0 Controller [Enabled]
UART1 Controller [Enabled]
UART2 Controller [Disabled]
Serial IO SPI1 Settings>
ChipSelect 0
polarity Sets initial polarity of
ChipSelect signal. Initial low is
with initial idle polarity of low.
[Active Low, Active High]
ChipSelect 1
polarity
Serial IO UART0 Settings> Hardware Flow
Control [Disabled]
Timing parameters disabled
Serial IO UART1 Settings>
Hardware Flow
Control [Disabled]
Timing parameters disabled
State After G3 Specifies the state to go to when power is reapplied after a power failure (G3 state).
[S0 State, S5 State]
Port 80h
Redirection Controls where the port 80h cycles are sent.
[LPC Bus, PCIE Bus]
Enhance Port
80h LPC
Decoding Supports the word/dword decoding of port 80h behind LPC.
[Enabled, Disabled]
Legacy IO Low
Latency Sets low latency of legacy IO.
Note: Some system requires lower IO latency irrespective of power. This is a tradeoff between
power and IO latency.
[Enabled, Disabled]
Timed GPIO0 Enables or disables Timed GPIO0
Note: disabled will disable cross time stamp time-synchronization as extension of Hammock
Harbor time synchronization.
[Enabled, Disabled]
Timed GPIO1 Enables or disables Timed GPIO1
Note: disabled will disable cross time stamp time-synchronization as extension of Hammock
Harbor time synchronization.
[Enabled, Disabled]
PCIe Ref PLL
SSCEN PCIe Ref PLL SC percentage, where Auto keeps hardware default
[Auto, 0.0%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%]
SPD Write Lock or release SPD write capability. For security recommendations, SPD write lock must be
set.
[Locked, Released]