SanDisk SDSDB-16 Product Manual Download Page 14

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Introduction to the SD Card

1-8

SD Memory Card

WP Group 1

WP Group 0

Block

Sector 1

Block

Sector 2

Sector 3

Sector n

WP Group n

Protected Area (Copyright protection)

Block

Sector 1

Block

Sector n

Figure 1-2. Memory Array Partitioning

Table 1-3. Memory Array Structures Summary

Part Number

Block Size

(Byte)

Data Area + Protected size

(Blocks)

Protected Area size

(Blocks)

User Area

(Blocks)

SDSDJ-1024 512

2,004,224

20,480

1,983,744

SDSDJ-512 512

1,001,104

10,240

940,864

SDSDJ-256 512

499,456

5,376

494,080

SDSDJ-128 512

248,640

2,624

246,016

SDSDJ-64 512

123,232

1,376

121,856

SDSDB-32 512

60,512

736

59,776

SDSDB-16 512

29,152

352

28,800

NOTE

: All measurements are in units per card.

Protected Area—The part of the Card that relates to the secured copyright management and has separate DOS
partitioning including sectors and blocks. The card write protection mechanism does not effect this area.

Summary of Contents for SDSDB-16

Page 1: ...ure Digital Card Product Manual Version 1 9 Document No 80 13 00169 December 2003 SanDisk Corporation Corporate Headquarters 140 Caspian Court Sunnyvale CA 94089 Phone 408 542 0500 Fax 408 542 0503 www sandisk com ...

Page 2: ...gistered trademarks of SanDisk Corporation Product names mentioned herein are for identification purposes only and may be trademarks and or registered trademarks of their respective companies 2003 SanDisk Corporation All rights reserved SanDisk products are covered or licensed under one or more of the following U S Patent Nos 5 070 032 5 095 344 5 168 465 5 172 338 5 198 380 5 200 959 5 268 318 5 ...

Page 3: ... 1 5 9 7 Data Transfer Rate 1 9 1 5 9 8 Data Protection in the Flash Card 1 10 1 5 9 9 Erase 1 10 1 5 9 10 Write Protection 1 10 1 5 9 11 Copy Bit 1 10 1 5 9 12 The CSD Register 1 10 1 5 10 SD Card SPI Mode 1 10 1 5 10 1 Negotiating Operating Conditions 1 11 1 5 10 2 Card Acquisition and Identification 1 11 1 5 10 3 Card Status 1 11 1 5 10 4 Memory Array Partitioning 1 11 1 5 10 5 Read and Write O...

Page 4: ...ocol Description 4 1 4 1 SD Bus Protocol 4 1 4 2 Protocol s Functional Description 4 4 4 3 Card Identification Mode 4 5 4 3 1 Reset 4 6 4 3 2 Operating Voltage Range Validation 4 7 4 3 3 Card Identification Process 4 7 4 4 Data Transfer Mode 4 8 4 4 1 Wide Bus Selection Deselection 4 10 4 4 2 Data Read Format 4 10 4 4 3 Data Write Format 4 11 4 4 4 Write Protect Management 4 13 4 4 4 1 Mechanical ...

Page 5: ...on Commands 5 8 5 2 SPI Command Set 5 8 5 2 1 Command Format 5 8 5 2 2 Command Classes 5 9 5 2 2 1 Detailed Command Description 5 9 5 2 3 Responses 5 12 5 2 3 1 Format R1 5 13 5 2 3 2 Format R1b 5 13 5 2 3 3 Format R2 5 13 5 2 3 4 Format R3 5 14 5 2 3 5 Data Response 5 15 5 2 4 Data Tokens 5 15 5 2 5 Data Error Token 5 16 5 2 6 Clearing Status Bits 5 16 5 3 Card Registers 5 16 5 4 SPI Bus Timing D...

Page 6: ...gital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION File System Support A 5 Appendix B Ordering Information B 1 Appendix C SanDisk Worldwide Sales Offices C 1 Appendix D Limited Warranty D 1 Appendix E Disclaimer of Liability E 1 ...

Page 7: ...iaCard forward compatibility was kept Actually the main difference between SD Card and MultiMediaCard is the initialization process The SD Card specifications were originally defined by MEI Matsushita Electric Company Toshiba Corporation and SanDisk Corporation Currently the specifications are controlled by the Secure Digital Association SDA The SanDisk SD Card was designed to be compatible with t...

Page 8: ...eatures The SD Card provides the following features Up to 1 GB of data storage SD Card protocol compatible Supports SPI Mode Targeted for portable and stationary applications for secured copyrights protected and non secured data storage Voltage range Basic communication CMD0 CMD15 CMD55 ACMD41 2 0 3 6V Other commands and memory access 2 7 3 6V Variable clock rate 0 25 MHZ Up to 12 5 MB sec data tr...

Page 9: ...atible with the following SD Card Physical Layer Specification standard The SD Card Physical Layer System Specification Version 1 01 This specification may be obtained from SD Card Association 53 Muckelemi St P O Box 189 San Juan Bautista CA 95045 0189 USA Phone 831 623 2107 Fax 831 623 2248 Email rcreech sdcard org http www sdcard org 1 5 Functional Description SanDisk SD Cards contain a high lev...

Page 10: ...ta space The SD Card s soft error rate specification is much better than the magnetic disk drive specification In the extremely rare case a read error does occur SD Cards have innovative algorithms to recover the data This is similar to using retries on a disk drive but is much more sophisticated The last line of defense is to employ a powerful ECC to correct the data If ECC is used to recover dat...

Page 11: ...the Erase Command The Erase sector or group command provides the capability to substantially increase the write performance of the SD Card Once a sector has been erased using the Erase command a write to that sector will be much faster This is because a normal write operation includes a separate sector erase prior to write 1 5 7 Automatic Sleep Mode A unique feature of the SanDisk SD Card and othe...

Page 12: ...cesses each card separately through its own command lines The SD Card s CID register is pre programmed with a unique card identification number which is used during the identification procedure In addition the SD Card host can read the card s CID register using the READ_CID SD Card command The CID register is programmed during the SD Card testing and formatting procedure on the manufacturing floor...

Page 13: ...ock command is sent by the host The size of a block is either programmable or fixed The information about allowed block sizes and the programmability is stored in the CSD The granularity of the erasable units is in general not the same as for the block oriented commands Sector The unit that is related to the erase commands Its size is the number of blocks that are erased in one portion The size of...

Page 14: ...mber Block Size Byte Data Area Protected size Blocks Protected Area size Blocks User Area Blocks SDSDJ 1024 512 2 004 224 20 480 1 983 744 SDSDJ 512 512 1 001 104 10 240 940 864 SDSDJ 256 512 499 456 5 376 494 080 SDSDJ 128 512 248 640 2 624 246 016 SDSDJ 64 512 123 232 1 376 121 856 SDSDB 32 512 60 512 736 59 776 SDSDB 16 512 29 152 352 28 800 NOTE All measurements are in units per card Protected...

Page 15: ... length for read operations is limited by the device sector size 512 bytes but can be as small as a single byte Misalignment is not allowed Every data block must be contained in a single physical sector The block length for write operations must be identical to the sector size and the start address aligned to a sector boundary Multiple Block Mode This mode is similar to the single block mode but t...

Page 16: ...to prevent the host from writing to or erasing data on the card The WP switch does not have any influence on the internal Permanent or Temporary WP bits in the CSD 1 5 9 11 Copy Bit The content of a SD Card can be marked as an original or a copy using the copy bit in the CSD register Once the Copy bit is set marked as a copy it cannot be cleared The Copy bit of the SD Card is programmed during tes...

Page 17: ...d detection methods can be found in SD Physical Specification s Application Notes given by the SDA 1 5 10 3 Card Status In SPI mode only 16 bits containing the errors relevant to SPI mode can be read out of the 32 bit SD Card status register The SD_STATUS can be read using ACMD13 the same as in SD Bus mode 1 5 10 4 Memory Array Partitioning Memory partitioning in SPI mode is equivalent to SD Bus m...

Page 18: ...ction to the SD Card 1 12 SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION 1 5 10 9 Write Protection Same as in SD Card mode 1 5 10 10 Copyright Protection Same as in SD Card mode ...

Page 19: ...Introduction to the SD Card SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION 1 13 This page intentionally left blank ...

Page 20: ...V Human body model according to ANSI EOS ESD S5 1 1998 8kV coupling plane discharge 15kV air discharge Human body model per IEC61000 4 2 2 2 Reliability and Durability Table 2 2 Reliability and Durability Specifications Durability 10 000 mating cycles Bending 10N Torque 0 15N m or 2 5 deg Drop Test 1 5m free fall UV Light Exposure UV 254nm 15Ws cm2 according to ISO 7816 1 Visual Inspection Shape a...

Page 21: ... Products 1 5msec 10msec 100msec 100msec Block Write Access Time Binary Products MLC Products 24msec 40msec 250msec 250msec CMD1 to Ready after power up 50msec 500msec Sleep to Ready 1msec 2msec NOTES All values quoted are under the following conditions 1 Voltage range 2 7 V to 3 6 V 2 Temperature range 25 C to 85 C 3 Are independent of the SD Card clock frequency 2 5 System Reliability and Mainte...

Page 22: ... 6 Physical Specifications Refer to Table 2 6 and to Figures 2 1 through 2 3 for SD Card physical specifications and dimensions Table 2 6 Physical Specifications Weight 2 0 g maximum Length 32mm 0 1mm Width 24mm 0 1mm Thickness 2 1mm 0 15mm in substrate area only 2 25mm maximum Figure 2 1 SD Card Dimensions ...

Page 23: ...Product Specifications 2 4 SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION Figure 2 2 SD Card Dimensions ...

Page 24: ...Product Specifications SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION 2 5 Figure 2 3 SD Card Dimensions ...

Page 25: ...Product Specifications 2 6 SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION This page intentionally left blank ...

Page 26: ... CLK I Clock 6 VSS2 S Supply voltage ground 7 DAT0 I O Data Line Bit 0 8 DAT1 I O Data Line Bit 1 9 DAT2 I O Data Line Bit 2 NOTES 1 S power supply I input O output using push pull drivers 2 The extended DAT lines DAT1 DAT3 are input on power up They start to operate as DAT lines after the SET_BUS_WIDTH command It is the responsibility of the host designer to connect external pullup resistors to a...

Page 27: ... consumption may occur due to the floating inputs Each card has a set of information registers refer to Table 3 3 Detailed descriptions are provided in Section 3 5 Table 3 3 SD Card Registers Name Width Description CID 128 Card identification number individual card number for identification RCA1 16 Relative card address local system address of a card dynamically suggested by the card and approved ...

Page 28: ...x communication lines and three supply lines CMD Command is a bi directional signal Host and card drivers are operating in push pull mode DAT0 3 Data lines are bi directional signals Host and card drivers are operating in push pull mode CLK Clock is a host to cards signal CLK operates in push pull mode VDD VDD is the power supply line for all cards VSS 1 2 VSS are two ground lines ...

Page 29: ...plify the handling of the card stack after initialization all commands may be sent concurrently to all cards Addressing information is provided in the command packet The SD Bus allows dynamic configuration of the number of data lines After power up by default the SD Card will use only DAT0 for data transfer After initialization the host can change the bus width number of active data lines This fea...

Page 30: ...removal insertion should be detected by the bus master using the CRC codes that suffix every bus transaction 3 2 1 Power Protection Cards can be inserted into or removed from the bus without damage If one of the supply pins VDD or VSS is not connected properly then the current is drawn through a data line to supply the card Data transfer operations are protected by CRC codes therefore any bit chan...

Page 31: ...S signal see Figure 3 4 The CS signal must be continuously active for the duration of the SPI transaction command response and data The only exception is card programming time At this time the host can de assert the CS signal without affecting the programming process The bi directional CMD and DAT lines are replaced by uni directional dataIn and dataOut signals This eliminates the ability of execu...

Page 32: ...contains a busy flag indicating that the card is still working on its power up procedure and is not ready for identification This bit informs the host that the card is not ready The host has to wait and continue to poll the cards each one on his turn until this bit is cleared The maximum period of power up procedure of single card shall not exceed 1 second Getting individual cards as well as the w...

Page 33: ... voltage differentials VSS1 VSS2 0 3 0 3 V Power up Time 250 mS From 0V to VDD Min 3 4 3 Bus Signal Line Load The total capacitance CL of the CLK line of the SD Card bus is the sum of the bus master capacitance CHOST the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line CL CHOST CBUS N CCARD Where N is the number of connected cards Requiring the sum of the h...

Page 34: ... Bus Signal Levels To meet the requirements of the JEDEC specification JESD8 1A the card input and output voltages shall be within the specified ranges in Table 3 6 for any VDD of the allowed voltage range Table 3 6 Input and Output Voltages Parameter Symbol Min Max Unit Conditions Output HIGH voltage VOH 0 75 VDD V IOH 100 µA VDD min Output LOW voltage VOL 0 125 VDD V IOL 100 µA VDD min Input HIG...

Page 35: ...es are referred to min VIH and max VIL Clock Frequency Data Transfer Mode fPP 0 25 MHz CL 100 pF 7 cards Clock Frequency Identification Mode The low frequency is required for MultiMediaCard compatibility fOD 0 1 100KHz 400 kHz CL 250 pF 21 cards Clock Low Time tWL 10 ns CL 100 pF 7 cards Clock High Time tWH 10 ns CL 100 pF 7 cards Clock Rise Time tTLH 10 ns CL 100 pF 10 cards Clock Fall Time tTHL ...

Page 36: ...nfiguration information The RCA register holds the card relative communication address for the current session The card status and SD status registers hold the communication protocol related status of the card 3 5 1 Operating Conditions Register OCR The 32 bit operation conditions register stores the VDD voltage profile of the card The SD Card is capable of executing the voltage recognition proced...

Page 37: ...bits are constant and will be set as described in Figure 4 8 If bit 32 the busy bit is set it informs the host that the card power up procedure is finished Figure 3 8 OCR Structure 3 5 2 Card Identification CID Register The CID register is 16 bytes long and contains a unique card identification number as shown in Table 3 9 It is programmed during card manufacturing and cannot be changed by SD Card...

Page 38: ... n is the most significant nibble and the m is the least significant nibble Example The PRV binary value filed for product revision 6 2 will be 0110 0010 The CRC Checksum is computed by the following formula CRC Calculation G x x7 3 1 M x MID MSB x119 CIN LSB x0 CRC 6 0 Remainder M x x7 G x 3 5 3 CSD Register The Card Specific Data CSD register contains configuration information required to access...

Page 39: ...evice size multiplier C_SIZE_MULT 3 R 49 47 SD128 64 SD064 32 SD032 32 SD016 32 SD008 16 100b 011b 011b 011b 010b erase single block enable ERASE_BLK_EN 1 R 46 46 Yes 1b erase sector size SECTOR_SIZE 7 R 45 39 32blocks 0011111b write protect group size WP_GRP_SIZE 7 R 38 32 128sectors 1111111b write protect group enable WP_GRP_ENABLE 1 R 31 31 Yes 1b Reserved for MultiMediaCard compatibility 2 R 3...

Page 40: ...5 5 D 6 0 E 7 0 F 8 0 7 Reserved NSAC Defines the worst case for the clock dependent factor of the data access time The unit for NSAC is 100 clock cycles Therefore the maximal value for the clock dependent part of the read access time is 25 5k clock cycles The total read access time NAC as expressed in the Table 5 17 is the sum of TAAC and NSAC It has to be computed by the host for the actual cloc...

Page 41: ...ers READ_BL_PARTIAL 1 means that smaller blocks can be used as well The minimum block size will be equal to minimum addressable unit one byte WRITE_BLK_MISALIGN Defines if the data block to be written by one command can be spread over more than one physical block of the memory device The size of the memory block is defined in WRITE_BL_LEN WRITE_BLK_MISALIGN 0 signals that crossing physical block b...

Page 42: ...CURR_MIN The maximum values for read and write currents at the minimal VDD power supply are coded in Table 3 17 Table 3 17 VDD Minimum Current Consumption VDD_R_CURR_MIN VDD_W_CURR_MIN Code For Current Consumption VDD 2 0 0 0 5mA 1 1mA 2 5mA 3 10mA 4 25mA 5 35mA 6 60mA 7 100mA VDD_R_CURR_MAX VDD_W_CURR_MAX The maximum values for read and write currents at the maximum VDD power supply are coded Tab...

Page 43: ...oup write protection possible R2W_FACTOR Defines the typical block program time as a multiple of the read access time Table 3 20 defines the field format Table 3 20 R2W_FACTOR R2W_FACTOR Multiples of Read Access Time 0 1 1 2 write half as fast as read 2 4 3 8 4 16 5 32 6 7 Reserved WRITE_BL_LEN The maximum write data block length is computed as 2WRITE_BL_LEN The maximum block length might therefor...

Page 44: ...ke file system with partition table 0 1 DOS FAT floppy like with boot sector only no partition table 0 2 Universal File Format 0 3 Others Unknown 1 0 1 2 3 Reserved CRC The CRC field carries the check sum for the CSD contents The checksum has to be recalculated by the host for any CSD modification The default corresponds to the initial CSD contents 3 5 4 SCR Register In addition to the CSD registe...

Page 45: ...s card vendor dependent SD_SECURITY Describes the security algorithm supported by the card Table 3 26 SD Supported Security Algorithm SD_SECURITY Supported Algorithm 0 No security 1 Security protocol 1 0 Security Spec Ver 0 96 2 Security protocol 2 0 Security Spec Ver 1 0 1 01 3 7 Reserved NOTE It is mandatory for a Writable SD Card OTP or R W to support Security Protocol SD_BUS_WIDTHS Describes a...

Page 46: ... A misaligned address that did not match the block length was used in the command C 29 BLOCK_LEN_ERROR E R 0 no error 1 error The transferred block length is not allowed for this card or the number of transferred bytes does not match the block length C 28 ERASE_SEQ_ERROR E R 0 no error 1 error An error in the sequence of erase commands occurred C 27 ERASE_PARAM E R X 0 no error 1 error An invalid ...

Page 47: ... the internal ECC A 13 ERASE_RESET S R 0 cleared 1 set An erase sequence was cleared before executing because an out of erase sequence command was received C 12 9 CURRENT_STATE S X 0 idle 1 ready 2 ident 3 stby 4 tran 5 data 6 rcv 7 prg 8 dis 9 15 reserved The state of the card when receiving the command If the command execution causes a state change it will be visible to the host in the response ...

Page 48: ...ned by the SET_BUS_WIDTH command A 509 SECURED_MODE S R 0 not in the mode 1 in secured mode Card is in Secured Mode of operation refer to the SD Security Specifications document A 508 496 Reserved 495 480 SD_CARD_TYPE S R 00xxh SD Memory Cards as defined in Physical Spec Ver 1 01 x don t care The following cards are currently defined 0000 Regular SD RD WR Card 0001 SD ROM Card In the future the 8 ...

Page 49: ...cessed by the host using the secured read write command after doing authentication as defined in the SD Security Specification The security protected area size is defined by SanDisk as approximately one percent of the total size of the card Tables 3 30 and 3 31 describe the user and protected areas for all SanDisk SD Cards Table 3 30 Parameters for User Area DOS Image Capacity Total LBAs No of Par...

Page 50: ...SD Card Interface Description SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION 3 25 This page intentionally left blank ...

Page 51: ... transferred via the data lines From host to card s CMD DAT Command From host to card Command Response From card to host Operation no response Operation no data Figure 4 1 No Response and No Data Operations Card addressing is implemented using a session address that is assigned to the card during the initialization phase The basic transaction on the SD bus is the command response transaction see F...

Page 52: ...t to card CMD DAT Command Data from card to host Command Response From card to host Block write operation Multiple block write operation Response Data stop operation Data block crc Data block crc Busy Stop command stops data transfer Busy crc OK response and busy from card Figure 4 3 Multiple Block Write Operation Command tokens have the coding scheme shown in Figure 4 4 Start bit always 0 0 1 Con...

Page 53: ...A R6 protected by 7 bit CRC checksum Transmitter bit 0 card response Total length 48 bits End bt always 1 0 0 Content CID or CSD CRC 1 Total length 136 bits End bt always 1 R1 R3 R6 R2 Figure 4 5 Response Token Format In the CMD line the MSB bit is transmitted first whereas the LSB bit is transmitted last When the wide bus option is used the data is transferred 4 bits at a time see Figure 4 6 Star...

Page 54: ...re intended for all SD Cards Some of these commands require a response Addressed Point to Point Commands The addressed commands are sent to the addressed SD Card and cause a response to be sent from this card A general overview of the command flow is shown in Figure 5 7 for the Card Identification Mode and in Figure 5 8 for the Data Transfer Mode The commands are listed in the command tables Table...

Page 55: ...eration modes and card states Each state in the SD Card state diagram Figures 4 7 and 4 8 is associated with one operation mode Table 4 1 Overview of Card States versus Operation Modes Card State Operation Mode Inactive State Inactive Idle State Ready State Card Identification Mode Identification State Stand by State Transfer State Sending data State Data Transfer Mode Receive data State Programmi...

Page 56: ... process starting at CMD1 SPI Operation Mode CMD0 CS Asserted 0 Figure 4 7 SD Card State Diagram Card Identification Mode 4 3 1 Reset GO_IDLE_STATE CMD0 is the software reset command and sets each SD Card to Idle State regardless of the current card state SD Cards in Inactive State are not affected by this command After power on by the host all SD Cards are in Idle State including the cards that w...

Page 57: ... SEND_OP_COND command CMD1 of MultiMediaCard The host should ignore an ILLEGAL_COMMAND status in the MultiMediaCard response to CMD3 since it is a residue of ACMD41 which is invalid in the MultiMediaCard CMD0 1 2 do not clear the status register Actually ACMD41 and CMD1 will be used by the host to distinguish between MultiMediaCard and SD Cards in a system By omitting the voltage range in the comm...

Page 58: ...uture data transfer mode typically with a higher clock rate than fOD Once the RCA is received the card state changes to the Stand by State At this point if the host wants the card to have another RCA number it may ask the card to publish a new number by sending another SEND_RELATIVE_ADDR command to the card The last published RCA is the actual RCA number of the card The host repeats the identifica...

Page 59: ...elative card address 0x0000 all cards transfer back to Stand by State Note that it is the responsibility of the Host to reserve the RCA 0 for card de selection refer to Table 4 3 CMD7 description This may be used before identifying new cards without resetting other already registered cards Cards that already have an RCA do not respond to identification commands ACMD41 CMD2 CMD3 in this state Impor...

Page 60: ...ually if the CMD and DAT0 lines of the cards are kept separated and the host keeps the busy DAT0 line disconnected from the other DAT0 lines of the other cards the host may access the other cards while the card is in busy Parameter set commands are not allowed while the card is programming Parameter set commands are set block length CMD16 erase block start CMD32 and erase block end CMD33 Read comm...

Page 61: ...rmat The data transfer format is similar to the data read format For block oriented write data transfer the CRC check bits are added to each data block The card performs a CRC check for each data line at the end of each received data block prior to a write operation The polynomial is the same one used for a read operation With this mechanism writing of erroneously transferred data can be prevented...

Page 62: ...till have the old data If the host sends a greater number of write blocks than are defined in ACMD23 the card will erase blocks one by one as new data is received This number will be reset to the default 1 value after Multiple Blocks Write operation It is recommended to use this command preceding CMD25 so that SanDisk s SD Card will be faster for Multiple Write Blocks operation Note that the host ...

Page 63: ...hed switch on the socket side will indicate to the host that the card is write protected or not It is the responsibility of the host to protect the card The position of the write protect switch is un known to the internal circuitry of the card 4 4 4 2 Card s Internal Write Protection Optional Card data may be protected against either erase or write The entire card may be permanently write protecte...

Page 64: ...ations and may not be used by any SD Card manufacturer ACMD6 ACMD13 ACMD17 25 ACMD38 49 ACMD51 General Command GEN_CMD CMD56 The bus transaction of the GEN_CMD is the same as the single block read or write commands CMD24 or CMD17 The difference is that the argument denotes the direction of the data transfer rather than the address and the data block is not memory payload data but has a vendor spec...

Page 65: ...on regardless of the host clock However the host must provide a clock edge for the card to turn off its busy signal Without a clock edge the SD Card unless previously disconnected by a deselect command CMD7 will force the DAT0 line down permanently 4 6 Cyclic Redundancy Codes CRC The Cyclic Redundancy Check CRC is intended for protecting SD Card commands responses and data transfer against transmi...

Page 66: ... xn second bit xn 1 last bit x0 CRC 15 0 Remainder M x x16 G x The first bit is the first data bit of the corresponding block The degree n of the polynomial denotes the number of bits of the data block decreased by one For example n 4 095 for a block length of 512 bytes The generator polynomial G x is a standard CCITT polynomial The code has a minimal distance d 4 and is used for a payload length ...

Page 67: ...r are card independent either 100 times longer than the typical access times for these operations given below or 100ms The times after which a time out condition for Write Erase operations occur are card independent either 100 times longer than the typical program times for these operations given below or 250ms A card shall complete the command within this time period or give up and return an erro...

Page 68: ...essed point to point Data Transfer Commands adtc data transfer on DAT All commands and responses are sent over the CMD line of the SD Card The command transmission always starts with the left bit of the bit string corresponding to the command code word 4 8 2 Command Format Command length 48 bits 1 92 µs 25 MHz 0 1 bit 5 bit 0 bit 31 bit 0 bit 6 bit 0 1 start bit host command argument CRC71 end bit...

Page 69: ...sses CCCs 0 1 2 3 4 5 6 7 8 9 11 Supported Commands Basic Reserved Block Read Reserved Block Write Erase Write Pro tection Lock Card Appli cation Specific Reserved CMD0 CMD2 CMD3 CMD4 CMD7 CMD9 CMD10 CMD12 CMD13 CMD15 CMD16 CMD17 CMD18 CMD24 CMD25 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD38 CMD42 CMD55 CMD56 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 ...

Page 70: ...address 0 deselects all When the RCA equals 0 the host may do one of the following use other RCA number to perform card de selection or re send CMD3 to change its RCA number to other then 0 and then use CMD7 with RCA 0 for card de selection CMD8 Reserved CMD9 ac 31 16 RCA 15 0 don t care R2 SEND_CSD Addressed card sends its card specific data CSD on the CMD line CMD10 ac 31 16 RCA 15 0 don t care ...

Page 71: ...ot Applicable CMD27 adtc 31 0 don t care R1 PROGRAM_CSD Programming of the programmable bits of the CSD The bit places must be filled but the value is irrelevant Table 4 6 Write Protection Class 6 Cmd Index Type Argument Resp Abbreviation Command Description CMD28 ac 31 0 data address R1b SET_WRITE_PROT This command sets the write protection bit of the addressed group The properties of write prote...

Page 72: ...4 8 Lock Card Commands Class 7 Cmd Index Type Argument Resp Abbreviation Command Description CMD42 CMD54 SDA Optional Commands currently supported by SanDisk SD Card Table 4 9 Application Specific Commands Class 8 CMD INDEX Type Argument Resp Abbreviation Command Description CMD55 ac 31 16 RCA 15 0 stuff bits R1 APP_CMD Indicates to the card that the next command is an application specific command...

Page 73: ...c 31 23 stuff bits 22 0 Number of blocks R1 SET_WR_BLK_ ERASE_COUNT Set the number of write blocks to be pre erased before writing to be used for faster Multiple Block WR command 1 default one wr block 2 ACMD24 Reserved ACMD25 Reserved for SD security applications 1 ACMD26 Reserved for SD security applications 1 ACMD38 Reserved for SD security applications 1 ACMD39 to ACMD40 Reserved ACMD41 bcr 31...

Page 74: ...t stby tran data rcv prg dis ina Command Changes to Class Independent CRC error command not sup ported Class 0 CMD0 idle idle idle idle idle idle idle idle idle CMD2 ident CMD3 stby stby CMD4 stby CMD7 card is addressed tran prg CMD7 card is not addressed stby stby stby dis CMD9 stby CMD10 stby CMD12 tran prg CMD13 stby tran data rcv prg dis CMD15 ina ina ina ina ina ina Class 2 CMD16 tran CMD17 d...

Page 75: ...cation ACMD41 card VDD range compatible ready ACMD41 card is busy idle ACMD41 card VDD range not compatible ina ACMD42 tran ACMD51 data class 9 11 CMD41 CMD43 CMD54 CMD57 CMD59 Reserved CMD60 CMD63 Reserved for manufacturer 4 10 Responses All responses are sent via the CMD line The response transmission always starts with the MSB The response length depends on the response type A response always s...

Page 76: ...sponse length 136 bits The content of the CID register is sent as a response to CMD2 and CMD10 The content of the CSD register is sent as a response to CMD9 Only bits 127 1 of the CID and CSD are transferred bit 0 of these registers is replaced by the end bit of the response Table 4 13 Response R2 Bit Position 135 134 133 128 127 1 0 Width bits 1 1 6 127 1 Value 0 0 111111 x 1 Description start bi...

Page 77: ...Care Data Bits from Card Repeater CRC Cyclic Redundancy Check Bits 7 Bits Card Active Host Active The difference between the P bit and Z bit is that a P bit is actively driven to HIGH by the card respectively host output driver while Z bit is driven to respectively kept HIGH by the pull up resistors RCMD respectively RDAT Actively driven P bits are less sensitive to noise All timing values are def...

Page 78: ...esponse CMD S T content CRC E Z Z P P S T content CRC E Z Z Z Figure 4 13 Command Response Timing Data Transfer Mode Last Card Response Next Host Command Timing After receiving the last card response the host can start the next command transmission after at least NRC clock cycles This timing is relevant for any host command Response NRC cycles Host command CMD S T content CRC E Z Z S T content CRC...

Page 79: ... D Figure 4 17 Timing of Multiple Block Read Command Host command NCR cycles Response CMD S T content CRC E Z Z P P S T content CRC E DAT D D D D D D E Z Z Figure 4 18 Timing of Stop Command CMD12 Data Transfer Mode 4 11 3 Data Write Single Block Write The host selects one card for data write operation by CMD7 The host sets the valid block length for block oriented data transfer by CMD16 The basic...

Page 80: ...en a flash programming error occurs the card will ignore all further data blocks In this case no CRC response will be sent to the host and therefore there will not be CRC start bit on the bus and the three CRC status bits will read 111 The data flow is terminated by a stop transmission command CMD12 Figure 4 20 describes the timing of the data blocks with and without card busy signal CardRsp CMD E...

Page 81: ...esponse Host Cmnd CMD S T content CRC E Z Z P P S T content CRC E S T Content Card is programming DAT S L L E Z Z Z Z Z Z Z Z Figure 4 23 Stop Transmission Received After Last Data Block Card is Busy Programming Host Command Ncr Cycles Card response Host Cmnd CMD S T content CRC E Z Z P P S T content CRC E S T Content Card is programming DAT Z Z Z Z Z Z Z Z Z Z Z S L L E Z Z Z Z Z Z Z Z Figure 4 2...

Page 82: ...ormation refer to Table 5 5 and 5 1 9 2 in Section 5 0 and the applications note in Appendix A Host Design Considerations NAND MMC and SD based Products Table 4 17 Timing Values Min Max Unit NCR 2 64 Clock Cycles NID 5 5 Clock Cycles NAC 2 See note Clock Cycles NRC 8 Clock Cycles NCC 8 Clock Cycles NWR 2 Clock Cycles NOTE min TAAC f NSAC 100 100ms f where units clocks and f is the clock frequency ...

Page 83: ...byte 1 5 1 1 Mode Selection The SD Card wakes up in the SD Bus mode It will enter SPI mode if the CS signal is asserted negative during the reception of the reset command CMD0 If the card recognizes that the SD Bus mode is required it will not respond to the command and remain in the SD Bus mode If SPI mode is required the card will switch to SPI mode and respond with the SPI mode R1 response The ...

Page 84: ...Data Read SPI mode supports single block and multiple block read operations SD Card CMD17 or CMD18 Upon reception of a valid read command the card will respond with a response token followed by a data token in the length defined in a previous SET_BLOCK_LENGTH CMD16 command see Figure 5 1 Figure 5 1 Single Block Read Operation A valid data block is suffixed with a 16 bit CRC generated by the standa...

Page 85: ...very data block has a prefix or start block token one byte After a data block is received the card will respond with a data response token and if the data block is received with no errors it will be programmed As long as the card is busy programming a continuous stream of busy tokens will be sent to the host effectively holding the dataOut line low Once the programming operation is completed the h...

Page 86: ...is the host s responsibility to prevent it 5 1 5 Erase and Write Protect Management The erase and write protect management procedures in the SPI mode are identical to the SD Bus mode While the card is erasing or changing the write protection bits of the predefined sector list it will be in a busy state and will hold the dataOut line low Figure 5 6 illustrates a no data bus transaction with and wit...

Page 87: ... completed its initialization processes and is ready for the next command In SPI mode however CMD1 has no operands and does not return the contents of the OCR register Instead the host can use CMD58 SPI Mode Only to read the OCR register It is the responsibility of the host to refrain from accessing cards that do not support its voltage range The use of CMD58 is not restricted to the initializatio...

Page 88: ... 1 CRC and Illegal Commands Unlike the SD Card protocol in SPI mode the card will always respond to a command The response indicates acceptance or rejection of the command A command may be rejected in any one of the following cases It is sent while the card is in read operation except CMD12 which is legal It is sent while the card is in Busy Card is locked and it is other than Class 0 or 7 command...

Page 89: ...SPI Protocol Definition SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION 5 7 ...

Page 90: ...ill be order of magnitude the number of write blocks WRITE_BL to be erased multiplied by the block write delay 5 1 10 Memory Array Partitioning Same as for SD Card mode 5 1 11 Card Lock Unlock The Card Lock Unlock feature is currently in the SanDisk SD Card 5 1 12 Application Specific Commands The Application Specific commands are identical to SD mode with the exception of the APP_CMD status bit s...

Page 91: ...e Card CMD Class CCC Class Description Supported Commands 0 1 9 10 12 13 16 17 18 24 25 27 28 29 30 32 33 38 42 55 56 58 59 class 0 Basic class 1 Not supported in SPI class 2 Block read class 3 Not supported in SPI class 4 Block write class 5 Erase class 6 Write protection Optional class 7 Lock Card Optional class 8 Application specific class 9 Not supported in SPI class 10 11 Reserved The Lock Ca...

Page 92: ...s read write 1 CMD17 Yes 31 0 data address R1 READ_SINGLE _BLOCK Reads a block of the size selected by the SET_BLOCKLEN command 2 CMD18 Yes 31 0 data address R1 READ_MULTIPLE _BLOCK Continuously transfers data blocks from card to host until interrupted by a STOP_ TRANSMISSION command CMD19 Reserved CMD20 No CMD21 CMD23 Reserved CMD24 Yes 31 0 data address R13 WRITE_BLOCK Writes a block of the size...

Page 93: ... the last write block in a continuous range to be erased CMD34 CMD37 Reserved CMD38 Yes 31 0 don t care R1b ERASE Erases all previously selected write blocks CMD39 No CMD40 No CMD41 CMD54 Reserved CMD55 Yes 31 0 stuff bits R1 APP_CMD Notifies the card that the next command is an application specific command rather than a standard command CMD56 Yes 31 0 stuff bits 0 RD WR 3 R1 GEN_CMD Used either t...

Page 94: ...write blocks to be pre erased before writing to be used for faster Multiple Block WR command 1 default one wr block 2 ACMD24 Reserved ACMD25 Yes Reserved for SD security applications1 ACMD26 Yes Reserved for SD security applications1 ACMD38 Yes Reserved for SD security applications1 ACMD39 to ACMD40 Reserved ACMD41 Yes None R1 SEND_OP_ COND Activates the card s initialization process ACMD42 Yes 31...

Page 95: ... error in the sequence of erase commands occurred Address error A misaligned address which did not match the block length was used in the command Parameter error The command s argument e g address block length was out of the allowed range for this card The structure of the R1 format is shown in Figure 5 7 7 In Idle State Erase Reset Illegal Command Com CRC Error Erase_Seq_Error 0 0 Address Error P...

Page 96: ...alid selection sectors for erase Write protect violation The command tried to write a write protected block Card ECC failed Card internal ECC was applied but failed to correct the data CC error Internal card controller error Error A general or an unknown error occurred during the operation Write protect erase skip Only partial address space was erased due to existing WP blocks Card is locked Suppo...

Page 97: ...ite Error response 110 the host may send CMD13 SEND_STATUS in order to get the cause of the write problem ACMD22 can be used to find the number of well written write blocks 5 2 4 Data Tokens Read and write commands have data transfers associated with them Data is being transmitted or received via data tokens All data bytes are transmitted MSB Data tokens are 4 to 515 bytes long and have the follow...

Page 98: ... 10 Data Error Token The four least significant bits LSB are the same error bits as in response format R2 5 2 6 Clearing Status Bits As described in the previous paragraphs in SPI mode status bits are reported to the host in three different formats response R1 response R2 and data error token the same bits may exist in multiple response types e g Card ECC failed As in the SD mode error bits are cl...

Page 99: ...and to Card Response Card is Busy The following timing diagram describes the command response transaction for commands when the card responses which the R1b response type e g SET_WRITE_PROT and ERASE When the card is signaling busy the host may deselect it by raising the CS at any time The card will release the DataOut line one clock after the CS going high To check if the card is still busy it ne...

Page 100: ...mand bus transaction The timeout values for the response and the data block are NCR Since the NAC is still unknown CS H L L L L L L H H H H NCS NEC DataIN X H H H H Read Command H H H H H H H H X X X X NCR NCR DataOut Z Z H H H H H H H H Card Response H H H H Data Block H H H H Z Z Z Figure 5 16 Reading the CSD Register 5 4 3 Data Write The host may deselect a card by raising the CS at any time du...

Page 101: ...ing Values Table 5 5 shows the timing values and definitions For more information refer to Table 4 17 in Section 4 0 Section 5 1 9 2 and the applications note in Appendix A Host Design Considerations NAND MMC and SD based Products Table 5 5 Timing Constants Definitions Min Max Unit NCS 0 8 Clock Cycles NCR 0 8 8 Clock Cycles NRC 1 8 Clock Cycles NAC 1 See Note 8 Clock Cycles NWR 1 8 Clock Cycles N...

Page 102: ...SPI Protocol Definition 5 20 SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION This page intentionally left blank ...

Page 103: ...us timing specifications If they want to support MultiMediaCards in their design the clock speed should be controllable by the host This is due to the MultiMediaCard s open drain mode the MultiMediaCard powers up in the open drain mode and cannot handle a clock faster than 400 Khz Once the MultiMediaCard completes the initialization process the card switches to the push pull mode In the push pull ...

Page 104: ...manufacturer products The SD Card also supports a 4 bit and a 1 bit SD bi directional bus mode SD bus pins are CLK CMD and DAT in 1 bit mode and CLK CMD and DAT 0 3 in 4 bit mode The MultiMediaCard also supports the 1 bit bi directional MMC bus mode that has CLK CMD and DAT bus pins The CMD and DAT pins are bi directional on the SD 1 bit SD 4 bit and MMC 1 bit The maximum burst rate achievable wit...

Page 105: ...t SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION A 3 The example in Table 3 shows the difference between moving 512 bytes of data to and from a MultiMediaCard or SD Card internal buffer using different bus modes ...

Page 106: ...r and recommended mode The more blocks that can be written in Multiblock mode the better the performance of the design Therefore when planning the design ensure that enough system RAM is designed in to support the multiblock capability The performance gain will always outweigh the cost of the extra RAM However if speed is not critical for example a data logger design that records only 512 bytes of...

Page 107: ...d writing to an SD Card and MultiMediaCard is generally done in 512 byte blocks however erasing often occurs in much larger blocks The NAND architecture used by SanDisk and other card vendors currently has Erase Block sizes of 32 or 64 512 byte blocks depending on card capacity In order to re write a single 512 byte block all other blocks belonging to the same Erase Block will be simultaneously er...

Page 108: ...3 SANDISK CORPORATION B 1 Appendix B Ordering Information To order SanDisk products directly from SanDisk call 408 542 0595 Secure Digital Card SDSDB 16 16 MB SDSDB 32 32 MB SDSDJ 64 64 MB SDSDJ 128 128 MB SDSDJ 256 256 MB SDSDJ 512 512 MB SDSDJ 1024 1024 MB ...

Page 109: ...ccount Sales 32500 Mills Rd Avon OH 44011 Tel 440 327 0490 Fax 440 327 0295 International Retail Sales European Retail Sales Wilhelminastraat 10 2011 VM Haarlem The Netherlands Tel 31 23 5514226 Fax 31 23 5348625 Southern European Retail Sales Centre Hoche Condorcet 3 Rue Condorcet B P 9 91263 Juvisy Sur Orge Cedex France Tel 33 169 12 16 04 Fax 33 169 12 16 24 Japan Retail Sales Umeda Shinmichi B...

Page 110: ...SanDisk Worldwide Sales Offices C 2 SanDisk Secure Digital SD Card Product Manual Rev 1 9 2003 SANDISK CORPORATION This page intentionally left blank ...

Page 111: ...und to be defective within one year of purchase SanDisk will have the option of repairing or replacing the defective product if the following conditions are met A The defective product is returned to SanDisk for failure analysis as soon as possible after the failure occurs B An incident card filled out by the user explaining the conditions of usage and the nature of the failure accompanies each re...

Page 112: ...efect conditions of use proof of purchase and purchase date If approved SanDisk will issue a Return Material Authorization or Product Repair Authorization number Ship the defective product to SanDisk Corporation Attn RMA Returns Reference RMA or PRA 140 Caspian Court Sunnyvale CA 94089 V STATE LAW RIGHTS SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES OR...

Page 113: ...where failure could cause damage injury or loss of life the products should only be incorporated in systems designed with appropriate redundancy fault tolerant or back up features SanDisk shall not be liable for any loss injury or damage caused by use of the Products in any of the following applications Special applications such as military related equipment nuclear reactor control and aerospace C...

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