SPI Protocol Definition
5-18
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
5.4.2. Data Read
The following timing diagram describes all single block read operations with the exception of SEND_CSD
command.
CS
H L L L
* * * * * * * * * * * * * * * * * * * * * * * * * * * *
L L L H H H H
<-N
CS
-> <-N
EC
->
DataIN
X H H H H Read Command H H H H H
* * * * * * * * * * * * * * * * * * * * * * * * *
H H H X X X X
<-N
CR
-> <-N
AC
->
DataOut
Z Z H H H H
* * * * * * * *
H H H H
Card Response
H H H H Data Block H H H H Z Z Z
Figure 5-14. Single Block Read Timing
The following table describes Stop transmission operation in case of Multiple Block Read.
CS
L L L L
* * * * * * * * * * * * * * * * * * * *
<- NCS ->
DataIN
X H H H H Stop Tran command H H H H H
* * * * ** * * *
<- NCR ->
DataOut
Data Transfer to host
H H
Card Response H
<2clk>
Figure 5-15. Multiple Block Read Timing
Reading the CSD Register
The following timing diagram describes the SEND_CSD command bus transaction. The timeout values for the
response and the data block are N
CR
(Since the N
AC
is still unknown).
CS
H L L L
* * * * * * * * * * * * * * * * * * *
L L L H H H H
<-
N
CS
->
<- N
EC
->
DataIN
X H H H H Read Command H H H H H
* * * * * * * * * * * * * * *
H H H X X X X
<- N
CR
->
<- N
CR
->
DataOut
Z Z H H H H
* * * * * * * *
H H H H
Card Response H H H H Data Block H H H H Z Z Z
Figure 5-16. Reading the CSD Register
5.4.3. Data Write
The host may deselect a card (by raising the CS) at any time during the card busy period (refer to the given timing
diagram). The card will release the DataOut line one clock after the CS going high. To check if the card is still busy
it needs to be re-selected by asserting (set to low) the CS signal.
The card will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.
CS
H L
* * * * * * * * * * * * * * * * * * *
L L L L L L L L H H H L L L L
<-N
CS
-> <-N
WR
-> <-N
EC
-> <-N
DS
->
DataIN
X H H H Write
Command H H H H H H H
Data
Block H H H H H H X X X H H H H
<-N
CR
->
DataOut
Z Z H H H * * * * * * * * H H H Card Resp H H H H H H H Data Resp
Busy
L Z Z Z Busy H
Figure 5-17. Device Write Timing
