Secure Digital (SD) Card Protocol Description
4-30
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
<-Host cmnd->
<- N
CR
->
<-Card
response
>
CMD
E Z Z P * P S T Content CRC E Z Z P
* * * * * * * * * * * * * * * *
P P P P P P P P
<-N
WR
->
<- Write data ->
CRC status
<- Busy ->
DAT0
Z Z
* * * * * *
Z Z Z * * * Z Z Z Z P * P S content CRC E Z Z S
Status E S L*L E Z
DAT1-3
Z Z
* * * * * *
Z Z Z * * * Z Z Z Z P * P S content CRC E Z Z X X X X X X X X X Z
Figure 4-19. Timing of the Block Write Command
Note that the CRC response output is always two clocks after the end of data.
If the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line to
LOW. The card stops pulling down the DAT0 line as soon as at least one receive buffer for the defined data transfer
block length becomes free. This signaling does not give any information about the data write status, which must be
polled by the host.
Multiple Block Write
In multiple block write mode, the card expects continuous flow of data blocks following the initial host write
command.
As in the case of single block write, the data is suffixed with CRC check bits to allow the card to check it for
transmission errors. The card sends back the CRC check result as a CRC status token on the DAT0 line. In the case
of transmission error the card sends a negative CRC status (‘101’). In the case of non-erroneous transmission the
card sends a positive CRC status (‘010’) and starts the data programming procedure. When a flash programming
error occurs the card will ignore all further data blocks. In this case no CRC response will be sent to the host and,
therefore, there will not be CRC start bit on the bus and the three CRC status bits will read (‘111‘).
The data flow is terminated by a stop transmission command (CMD12). Figure 4-20 describes the timing of the data
blocks with and without card busy signal.
<-CardRsp->
CMD
E Z Z P
* * * * * * * * * * * * * * *
P P P P P
* * * * * * * * * * * * * * *
P P P P P P P P P
<-N
WR
->
<- Write data ->
CRC status <-N
WR
->
<- Write data ->
CRC status <- Busy -> <-N
WR
->
DAT
Z Z P * P S Data+CRC
E Z Z S Status E Z P * P S Data+CRC
E Z Z S Status E S L*L E Z P*P
Figure 4-20. Timing of the Multiple Block Write Command
The stop transmission command works similar as in the read mode. Figures 4-21 through 4-24 describe the timing
of the stop command in different card states.
<---- Host Command ---->
< N
cr
Cycles >
<----- Card response----->
<Host Cmnd>
CMD
S T
content
CRC E Z Z P
P * * * * * * P
S T
content
CRC E
S T
Content
<----------
Card
is
programming
---------->
DAT
D D D D D D D D D D E Z Z S L
* * * * * * * * * * * * * * * * * * * * *
E Z Z Z Z Z Z Z Z
Figure 4-21. Stop Transmission During Data Transfer from the Host
The card will treat a data block as successfully received and ready for programming only if the CRC data of the
block was validated and the CRC status token sent back to the host. Figure 4-22 is an example of an interrupted (by
a host stop command) attempt to transmit the CRC status block. The sequence is identical to all other stop
transmission examples. The end bit of the host command is followed, on the data line, with one more data bit, end
bit and two Z clock for switching the bus direction. The received data block, in this case is considered incomplete
and will not be programmed.
