Chapter 3 – iNAND Interface Description
Revision 3.1
SanDisk iNAND Product Manual
© 2006 SanDisk Corporation
3-3
12/07/06
3.3 Electrical
Interface
The power scheme of SanDisk iNAND is handled locally in each card and in the bus
master. Refer to
Section 6.4
of the SDA
Physical Layer Specification
,
Version 2.00
.
3.3.1 Power
Up
Refer to
Section 6.4.1
of the SDA
Physical Layer Specification, Version 2.00
.
3.3.2
Bus Operating Conditions
SPI Mode bus operating conditions are identical to SD Bus Mode operating conditions. For
details, see
Section 6.6
of the SDA
Physical Layer Specification
,
Version 2.00
.
3.3.3
Bus Timing (Default)
See
Section 6.7
of the SDA
Physical Layer Specification, Version 2.00.
3.3.4
Bus Timing (High-Speed Mode)
See
Section 6.8
of the SDA
Physical Layer Specification, Version 2.00
.
3.4 iNAND
Registers
There is a set of eight registers within the iNAND interface. For specific information about
each register, refer to
Section 5
of the SDA
Physical Layer Specification, Version 2.00
.
3.4.1 Operating
Conditions
Register
The
Operation Conditions Register
(OCR)
stores the VDD voltage profile for iNAND.
Refer to
Section 5.1
of the SDA
Physical Layer Specification
,
Version 2.00
.
3.4.2 Card
Identification
Register
The
Card Identification (CID)
Register
is 16 bytes long and contains the unique card
identification number. It is programmed during manufacturing and cannot be changed by
iNAND hosts. See Table 3-3.
