UP1500 User’s Manual
Chapter 2 System Configuration
UP1500 800-A1
2-7
2.4
Initialization Strapping
The UP1500 has another two switchpacks - SW2, SW3 - which describe the
strapping of the AMD-761 System Controller.
2.4.1
System Clock Speed
System clock speed is encoded using Switches 1 and 2 of SW2.
2.4.2
Disable Divider
Special clock test mode that accomodates a large skew between the 1X and 2X
clocks is enabled using Switch 3 of SW2.
2.4.3
Inclk Delay Enable
Inclock delay of the AMD-761 System Controller is enabled using Switch 4 of
SW2.
2.4.4
CPU Clk Hist
Amount of hysteresis applied to the SysDataOutClk[3:0] and SysAddOutClk
inputs for noise immunity is encoded using Switches 5 and 6 of SW2.
2.4.5
AGP Clk MUX
Input to APLL clock mux for PLL test mode is selected using Switches 7 and 8 of
SW2 and Switch 1 of SW3.
